参数资料
型号: IPR-POSPHY4
厂商: Altera
文件页数: 111/144页
文件大小: 0K
描述: IP POS-PHY L4 RENEW
标准包装: 1
系列: *
类型: MegaCore
功能: POS-PHY 4 级接口,链路层/物理层
许可证: 续用许可证
A. Start-Up Sequence
This appendix applies to any SPI-4.2 transmitter and receiver pair, where at least one
is an Altera ? POS-PHY Level 4 MegaCore ? function.
Figure A–1. Start-Up Sequence Flowchart
Power up
Assert all resets
RX sends 'b11 status
(1)
TX system clocks
stabilize
(2a)
TX PL4 clocks
stabilize
(2b)
RX PL4 clocks
stabilize
(2b)
RX system clocks
stabilize
(2a)
Release TX core reset
and
disable status FSM
(3)
TX sends trainin g
(3)
Release RX core reset
and
disable status FSM
(3)
Confi g ure TX function
and
enable status FSM
(4)
RX DPA
stabilized and trained
(5a)
Confi g ure RX function
and
enable status FSM
(4)
RX ready
Sends status frames
(6)
TX frames on status
TX ready
(6)
The startup sequence combines clock stabilization, reset, and configuration with the
training and framing aspects of the SPI-4.2 protocol as shown in Figure A–1 on
page A–1 . Details of each event as they happen in the POS-PHY Level 4 MegaCore
function are listed in Table A–1 , but similar events should happen in other SPI-4.2
implementations.
May 2013
Altera Corporation
POS-PHY Level 4 MegaCore Function User Guide
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