参数资料
型号: IPR-POSPHY4
厂商: Altera
文件页数: 106/144页
文件大小: 0K
描述: IP POS-PHY L4 RENEW
标准包装: 1
系列: *
类型: MegaCore
功能: POS-PHY 4 级接口,链路层/物理层
许可证: 续用许可证
6–6
Chapter 6: Testbench
Transmitter Testbench Description
Table 6–4. Error Simulation Using the Testbench Module (Part 2 of 2)
Error Signal
err_rd_dip4
err_rd_pr
err_rd_sob
err_rd_sop8
err_rd_tp
Testbench Simulation
Using the pkt2 task, send in packets with error code 9:
spi_gen.pkt2( <port> ,/*err*/9, <size> , <pkt_num> );
This is a catch all error for miscellaneous protocol errors. For example, a payload control word
followed by a payload control word:
spi_gen.cw2(1'b1,1'b00,1'b1,8'h05,1'b0); // Payload control word with SOP
for port 5
spi_gen.cw2(1'b1,1'b00,1'b0,8'h02,1'b0); // Payload control word with
Continue for port 2
Send in a data burst that is not properly started, with a payload control word:
spi_gen.cw2(1'b0,1'b00,1'b0,8'h03,1'b0); // Control word without payload
cw bit
set spi_gen.pay(16'h1234);
spi_gen.pay(16'h4567);
Send in packets with SOPs less than 8 cycles apart:
spi_gen.cw2(/*cw_type*/1'b1,/*eop*/2'b00,/*sop*/1'b1, <port> ,/*dip4err*/1'b0
);
spi_gen.pay(16'h1234);
spi_gen.pay(16'h4567);
spi_gen.cw2(/*cw_type*/1'b1,/*eop*/2'b00,/*sop*/1'b1, <port> ,/*dip4err*/1'b0
);
spi_gen.pay(16'h89ab);
spi_gen.pay(16'hcdef);
Send in a corrupted training pattern:
repeat (10) spi_gen.cw(16'h0FFF,1'b0); // Send 10 training control word
repeat (99) spi_gen.pay(16'h000F); // Create a tp error with 99 training
data words
Only works after the MegaCore function is aligned with DPA.
Transmitter Testbench Description
The testbench provided with the transmitter variations of the POS-PHY Level 4
MegaCore function tests the following functions:
Using the Avalon-MM interface, programs the calendar if Asymmetric Port
Support is turned on (refer to Appendix E .)
Synchronization of the MegaCore function with a training pattern
Data integrity from the Atlantic back-end interface through the user ’s
configuration to the SPI-4.2 interface
Sends data from multiple ports to the SPI-4.2 interface
Verifies that the MegaCore function responds to backpressure on the SPI-4.2
interface (this test can be turned on and off)
POS-PHY Level 4 MegaCore Function User Guide
May 2013 Altera Corporation
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参数描述
IPR-QDRII/UNI 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-RAPIDIOII 功能描述:开发软件 RapidIO 1x/2x/4x MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-RIOPHY 功能描述:开发软件 RapidIO MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-RLDII/UNI 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-RLDRAMII 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors