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| 型号： | IPR-POSPHY4 |
| 厂商： | Altera |
| 文件页数： | 93/144页 |
| 文件大小： | 0K |
| 描述： | IP POS-PHY L4 RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | POS-PHY 4 级接口，链路层/物理层 |
| 许可证： | 续用许可证 |
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Chapter 5: Functional Description—Transmitter
Signals
Table 5–7. SPI-4.2 Status Channel Control and Status (Part 3 of 3)
5–21
Signal
Direction
Clock Domain
Description
Indicates the frame was malformed. Possible causes
are:
■
Calendar did not begin with a framing word.
err_ts_frm
Output
■
■
Hitless bandwidth repositioning is turned on, and
calendar select word was not ‘b01 or ‘b10 .
Unexpected framing word was in the calendar
portion of the frame.
Asserted synchronous to stat_ts_dip2state .
Indicates the calculated DIP-2 did not match the DIP-
err_ts_dip2
Output
2 word in the status frame. Asserted synchronous to
stat_ts_dip2state .
Sets the expected length of the calendar in the status
frame. This port is absent if Asymmetric Port
ctl_ts_callen[7:0]
Input
tsclk
Support is turned on. Only change at reset, or when
ctl_ts_rsfrm and stat_ts_disabled are both
asserted.
Sets the expected number of status calendar
repetitions between framing and DIP-2 in the status
ctl_ts_calm[7:0]
stat_ts_calsel
tav_clk
Input
Output
Input
frame. This port is absent if Asymmetric Port
Support is turned on. Only change at reset, or when
ctl_ts_rsfrm and stat_ts_disabled are both
asserted.
Indicates the currently selected calendar when
Hitless B/W reprovisioning is turned on. Zero
indicates ‘b01 , and one indicates ‘b10 . It is set to
zero when Hitless B/W reprovisioning is turned off.
This port is absent if Asymmetric Port Support is
turned off.
Avalon-MM clock. Signals prefixed by tav_ are
synchronous to this clock. This port is absent if
Asymmetric Port Support is turned off.
tav_address[3:0]
tav_chipselect
tav_write
tav_read
tav_writedata[15:0]
tav_readdata[15:0]
tav_waitrequest
May 2013
Altera Corporation
Input
Input
Input
Input
Input
Output
Output
tav_clk
tav_clk
Avalon-MM address. This port is absent if
Asymmetric Port Support is turned off.
Avalon-MM chip select. This port is absent if
Asymmetric Port Support is turned off.
Avalon-MM write enable. This port is absent if
Asymmetric Port Support is turned off.
Avalon-MM read enable. This port is absent if
Asymmetric Port Support is turned off.
Avalon-MM write data. This port is absent if
Asymmetric Port Support is turned off.
Avalon-MM read data. This port is absent if
Asymmetric Port Support is turned off.
Avalon-MM wait request. This port is absent if
Asymmetric Port Support is turned off.
POS-PHY Level 4 MegaCore Function User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-QDRII/UNI | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RAPIDIOII | 功能描述:开发软件 RapidIO 1x/2x/4x MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RIOPHY | 功能描述:开发软件 RapidIO MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RLDII/UNI | 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RLDRAMII | 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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