参数资料
型号: IPR-POSPHY4
厂商: Altera
文件页数: 98/144页
文件大小: 0K
描述: IP POS-PHY L4 RENEW
标准包装: 1
系列: *
类型: MegaCore
功能: POS-PHY 4 级接口,链路层/物理层
许可证: 续用许可证
5–26
Chapter 5: Functional Description—Transmitter
Latency Information
Latency Information
The transmitter MegaCore functions involve two kinds of latency: data latency and
status receive latency.
Data latency is defined as the latency from the Atlantic interface that is reading from
the buffer to the SPI-4.2 LVDS transmit pins. It does not include the latency through
the buffer. For external status, the numbers assume that the aN_atxclk is faster than
the tsclk thus ensuring that the clock-crossing FIFO buffer is empty.
Status receive latency is defined as the latency from the point at which the last cycle of
a valid status message is received (the DIP-2 error code) to the point at which the user
logic or the transmit scheduler can use the status information. It does not include the
time spent waiting for a complete, error-free status message.
Figure 5–12 shows a generic picture of the L MAX contributions (transmitter start to
transmitter finish gives the transmitter L MAX ).
Figure 5–12. L MAX Top Level Overview
POS-PHY Level 4 MegaCore Function User Guide
May 2013 Altera Corporation
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IPR-RAPIDIOII 功能描述:开发软件 RapidIO 1x/2x/4x MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-RIOPHY 功能描述:开发软件 RapidIO MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-RLDII/UNI 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-RLDRAMII 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors