参数资料
型号: IPR-POSPHY4
厂商: Altera
文件页数: 118/144页
文件大小: 0K
描述: IP POS-PHY L4 RENEW
标准包装: 1
系列: *
类型: MegaCore
功能: POS-PHY 4 级接口,链路层/物理层
许可证: 续用许可证
B–2
1
Appendix B: Sharing PLLs for Multicore Designs
4. Open the transmitter ’s LVDS MegaWizard Plug-In and change the input clock
frequency to < number of Mbps >/2 (refer to Figure B–2 ).
Figure B–2. Specify ALTLVDS Parameters
5. In the top-level design, connect the PLL reset signals ( cH_rx_pll_areset and
cH_tx_pll_areset ) and the rdclk to the trefclk signal.
To share a PLL between two transmitters, ensure the input frequencies are matched
and connect the trefclk signals together.
If the receiver PLL is configured as real-time configurable, it does not automatically
merge with the transmitter PLL. Use the following assignment to force the merging of
the receiver and transmitter PLLs:
set_instance_assignment -name FORCE_MERGE_PLL ON -from "< tx_pll >" -to
"< rx_pll >"
POS-PHY Level 4 MegaCore Function User Guide
May 2013 Altera Corporation
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