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参数资料
| 型号： | IPR-POSPHY4 |
| 厂商： | Altera |
| 文件页数： | 74/144页 |
| 文件大小： | 0K |
| 描述： | IP POS-PHY L4 RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | POS-PHY 4 级接口，链路层/物理层 |
| 许可证： | 续用许可证 |
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5–2
Chapter 5: Functional Description—Transmitter
Block Description
This section describes the top-level blocks of the POS-PHY Level 4 transmitter
MegaCore function.
Atlantic Buffers
The Atlantic FIFO buffers provide the following features:
■
■
■
■
■
Slave-sink Atlantic interface on the user side
Configurable buffer size
Multiple clock domain support
Overflow error indication and FIFO buffer empty indication
Atlantic interface error checking
■
■
Missing or spurious start-of-packet (SOP)/end-of-packet (EOP) detection and
correction
Optional overflow handling
For a complete single-PHY implementation, two modes are possible: individual
buffers with the number of ports = 1, or a shared buffer with embedded addressing
with the number of ports = 1. In the individual buffers mode, the credit-based flow-
control scheduler is included.
1
Only single-PHY applications that require the more sophisticated credit-based
scheduler should select the individual buffers mode, because the shared buffer with
embedded addressing mode has a simpler backpressure mechanism.
Shared Buffer with Embedded Addressing
When you turn on turn on Shared Buffer with Embedded Addressing , the POS-PHY
Level 4 MegaCore function consists of a shared buffer with embedded addressing,
and the transmitter processor logic.
The shared buffer is a single Atlantic FIFO buffer, where for each data word a tag is
carried containing the port number. There is no transmit scheduler provided with this
mode; the data is simply pulled from the buffer and transmitted in the same order it
was pushed in. This means that the order in which data bursts are transmitted on the
SPI-4.2 bus is dictated by the order in which the user logic writes data to the FIFO
buffer. The user logic is responsible for scheduling the transmit data and pushing it
into the transmitter buffers so that it is SPI-4.2 compliant (including ensuring that
burst sizes are properly maintained).
The shared FIFO buffer and the logic support up to 256 ports. If the Atlantic error
checking feature is turned on, the logic for error checking supports the number of
ports chosen as a parameter. The port width field remains fixed for 256 ports, and if
packets for ports beyond the number of ports parameter are pushed into the transmit
buffer, they are transmitted but are not checked for errors. All address bits are passed
through the buffer unaffected
The shared buffer with embedded addressing mode supports two different
backpressure mechanisms.
POS-PHY Level 4 MegaCore Function User Guide
May 2013 Altera Corporation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-QDRII/UNI | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RAPIDIOII | 功能描述:开发软件 RapidIO 1x/2x/4x MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RIOPHY | 功能描述:开发软件 RapidIO MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RLDII/UNI | 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RLDRAMII | 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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