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| 型号： | IPR-POSPHY4 |
| 厂商： | Altera |
| 文件页数： | 35/144页 |
| 文件大小： | 0K |
| 描述： | IP POS-PHY L4 RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | POS-PHY 4 级接口，链路层/物理层 |
| 许可证： | 续用许可证 |
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Chapter 3: Parameter Settings
3–13
Protocol Parameters
To be effective, the far-end scheduler must handle received status optimistically. As
status is received, credits for each port are topped up to MaxBurst1 / MaxBurst2
levels.
Turn on Asymmetric Port Support to instantiate an Avalon ? Memory-Mapped
(Avalon-MM) interface in the MegaCore function. The Avalon-MM interface
programs the values of calendar length, calendar multiplier, and the port numbers for
each of the calendar slots.
If you turn on Asymmetric Port Support , the calendar length is programmed from
the Avalon-MM interface (refer to Appendix E ).
If you turn on Programmable calendar length , a calendar length input pin is added to
the MegaCore function. This pin allows you to vary the calendar length value from
one to the number of ports without having to recompile. If the programmable
calendar length support parameter is turned off, the calendar length is equal to the
number of ports.
The calendar length value cannot be greater than the number of ports (except when
you turn on Asymmetrical Port Support ).
The Calendar multiplier determines the number of times the calendar sequence is
repeated before the DIP-2 parity and framing is inserted. Choose a value from 1 to
256.
If the Asymmetric Port Support is turned on, the calendar multiplier value is
programmed via the Avalon-MM interface.
1
The calendar multiplier × calendar length value must be set according to the
instructions in Table C–1 on page C–1 of the “Clock Structure” section, otherwise the
status channel does not operate correctly.
The Maximum calendar length (only available when you turn on Asymmetric Port
Support) defines the maximum number of calendar entries available in the
configurable calendar. Choose a value from 32 to 2,048.
When you turn on Hitless B/W Reprovisioning (only available when you turn on
Asymmetric Port Support) , the receiver can transmit a calendar-select word in the
status frame. Active and inactive calendars are tied to the current calendar-select
word in the receiver. When the current calendar-select word changes, the active and
inactive calendars are swapped at the appropriate time, in the following order:
■
■
■
■
■
The CALSEL_REQ register bit is toggled at the receiver (refer to page 4–30 ).
At the beginning of the next status frame, the calendar-select word is toggled.
The receiver toggles the used calendar multiplier, calendar length, and calendar to
transmit the next status frame.
The transmitter receives the first calendar-select word of the new frame and
detects the toggle.
The transmitter toggles the used calendar multiplier, calendar length, and
calendar to interpret the next status frame.
May 2013
Altera Corporation
POS-PHY Level 4 MegaCore Function User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-QDRII/UNI | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RAPIDIOII | 功能描述:开发软件 RapidIO 1x/2x/4x MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RIOPHY | 功能描述:开发软件 RapidIO MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RLDII/UNI | 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-RLDRAMII | 功能描述:开发软件 RLDRAM II Controller MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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