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参数资料
| 型号： | M66596WG |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封装： | 0.80 MM PITCH, FBGA-64 |
| 文件页数： | 108/133页 |
| 文件大小： | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 74 of 127
The controller may carry out writing to the PID bit, depending on the results of the transaction.
(1)
Host mode
(a) NAK setting
:
In the following cases, it becomes "PID=NAK" and issue of a token is stopped automatically.
- When a peripheral device ignores the token other than isochronous transfer.
- When the packet which is not normal is received during transmission other than isocronous transfer.
- When a short packet is received, if the SHTNAK bit of the PIPECFG register has been set to “1” for bulk
transfer,
- When the transaction counter has ended, if the SHTNAK bit of the PIPECFG register has been set to “1” for
bulk transfers.
(b) BUF setting
The controller doesn’t set up “PID=BUF”.
(c)
STALL setting :
In the following cases, it becomes "PID=STALL" and issue of a token is stopped automatically.
- When the “STALL” packet from a peripheral device is received..
- When an error has been detected in a received data packet indicating that the data size
exceeds the maximum packet size
(2)
Peripheral mode
(a) NAK setting
:
- When the SETUP token is received normally (DCP only)
- When a short packet is received, if the SHTNAK bit of the PIPECFG register has been set to “1” for bulk
transfers
- When the transaction counter has ended, if the SHTNAK bit of the PIPECFG register has been set to “1” for
bulk transfers
(b) STALL setting :
- When an error has been detected in a received data packet indicating that the data size
exceeds the maximum packet size
- When a control transfer stage transition error has been detected
3.3.5 Registers that should not be set in the USB communication enabled (“PID=BUF”) state
ISEL
bit of the CFIFOSEL
register (applies only when DCP is selected)
TGL
and SCLR bits of the CFIFOSIE
register
DCLRM
, TRENB, TRCLR, and DEZPM bits of the DxFIFOSEL register
TRNCNT
bit of the DxFIFOTRN register
The various bits of the DCPCFG
and DCPMAXP registers
The various bits of the DCPCTR
register (except for the CCPL bit)
The various bits of the PIPECFG
, PIPEBUF, and PIPEMAXP registers
The various bits of the PIPEPERI
and PIPExCTR registers
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