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参数资料
型号： M66596WG
元件分类： 总线控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封装： 0.80 MM PITCH, FBGA-64
文件页数： 58/133页
文件大小： 1611K
代理商： M66596WG
M66596FP/WG
rev .1.00
2006.3.14
page 28 of 127
CFIFO port control register [CFIFOCTR]
<Address: 20H>
D0FIFO port control register [D0FIFOCTR]
<Address: 26H>
D1FIFO port control register [D1FIFOCTR]
<Address: 2CH>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BVAL
BCLR
FRDY
DTLN
0
-
0
-
0
-
0
?
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
Bit
Name
Function
S/W
H/W
Note
15 BVAL
Buffer Memory Valid flag
0: Invalid
1: Writing ended
R/ W(1) R/W
3.4.2
*7)
14 BCLR
CPU Buffer Clear
0: Invalid
1: Clears the buffer memory on the CPU side.
R(0)/
W(1)
R/W(0) 3.4.2
*8), *9)
13 FRDY
FIFO Port Ready
0: FIFO port access is disabled.
1: The FIFO port can be accessed.
R
W
3.4.4
*10)
12 Nothing is placed here. This should be fixed at “0”.
11-0 DTLN
Reception Data Length
The length of the reception data can be
confirmed.
R
W
3.4.4
*8)
<<Notes>>
*7) Writing “1” to the BVAL bit is valid when the direction of the data packet is the sending direction (when data is
being written to the buffer memory). When the direction is the receiving direction, “BVAL=0” should be set.
*8) The BCLR bit and DTLN bit are valid for the buffer memory on the CPU side. Software should set “BCLR=1” or
refer DTLN bit after making sure that “FRDY=1”.
*9) Using the BCLR bit to clear the buffer should be done with the pipe invalid state by the pipe configuration
(“PID=NAK”).
*10) The FRDY bit requires an access cycle of at least 450 ns after the pipe has been selected.
CFIFO port SIE register [CFIFOSIE]
<Address: 22H>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TGL
SCLR SBUSY
0
-
0
-
0
-
0
?
Bit
Name
Function
S/W
H/W
Note
15 TGL
Access Right Switch
0: Invalid
1: Switches access right
R(0)/
W(1)
R/W(0) 3.4.2.3
*11)
14 SCLR
SIE Buffer Clear
0: Invalid
1: Clears buffer memory on SIE side
R(0)/
W(1)
R/W(0) 3.4.2.4
*12)
13 SBUSY
SIE Buffer Busy
0: SIE is not being accessed.
1: SIE is being accessed.
R
W
3.4.2.3
12-0 Nothing is placed here. These should be fixed at “0”.
<<Note>>
*11) The function of the TGL bit is to set the buffer memory on the SIE side to the CPU side. Set “PID=NAK” and
check the SBUSY bit to make sure the SIE is not accessing the buffer (“SBUSY=0”). Then write the TGL bit
(toggle operation). This bit is valid only for pipes for which the reception direction (reading from the buffer
memory) has been set.
*12) The function of the SCLR bit is to clear the buffer memory on the SIE side. Set “PID=NAK” and check the
SBUSY
bit to make sure the SIE is not accessing the buffer (“SBUSY=0”). Then clear the buffer. This bit is
valid only for pipes for which the sending direction (writing to the buffer memory) has been set.
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