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| 型号： | M66596WG |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封装： | 0.80 MM PITCH, FBGA-64 |
| 文件页数： | 122/133页 |
| 文件大小： | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 87 of 127
3.6 Control transfers (DCP)
Data transfers of the data stage of control transfers are done using the default control pipe (DCP). The DCP buffer
memory is a 256-byte single buffer, and is a fixed area that is shared for both control reading and control writing.
The buffer memory can be accessed through the CFIFO port.
3.6.1
Host mode
3.6.1.1 Setup stage
S/W writes the data of an setup packet in USBREG register, USBVAL register, USBINDX register, and USBLENG
register. The controller transmits an setup packet by writing 1 in the SUREQ bit of DCPCTR register. After a
transaction ends the "SUREQ" bit, a controller writes in "0". During "SUREQ =1" does not operate the USB request
registers. The device address of a setup transaction is specified in the DEVSEL bit of a DCPMAXP register.
If the response from peripheral is received, the controller generates interrupt request (the SIGN bit or SACK bit of
INTSTS1
register). S/W can check a setup transaction result by these interrupt request.
The data packet of a setup transaction is always transmitted as DATA0.
3.6.1.2 Data stage
Communication of a data stage uses a DCP buffer memory. S/W sets up the access direction in the ISEL bit of a
CFIFOSEL
register. Moreover, set up the transmission direction in the DIR bit of a DCPCFG register.
The 1st data packet of a data stage needs to communicate considering Data PID as DATA1. Data PID is set to
DATA1 by the SQSET bit of a DCPCFG register, and a transaction is performed by setting a PID bit as BUF. S/W
detects completion of data transmission by BRDY interruption and BEMP interruption. Data transmission of two or
more packets is possible by setting up continuous transfer mode. However, in the case of the receiving direction,
unless it becomes buffer full or receives a short packet, BRDY interruption does not occur.
Moreover, in control write transmission, control the last packet to become a short packet containing a Zero-Length
packet by S/W.
In the case of the data transmitting direction at the time of Hi-Speed communication, a PING packet is
transmitted. Control of a PING packet is the same as that of a bulk transfer. Please refer to Chapter 3.7.1.
3.6.1.3 Status stage
A status stage is data transmission of the Zero-Length packet. The communication direction is opposite to a data
stage. It is the data transmission which used the DCP buffer memory. A transaction is performed in the same
procedure as a data stage.
The 1st data packet of a status stage needs to communicate considering Data PID as DATA1. Data PID is set to
DATA1 by the SQSET bit of a DCPCFG register.
Reception of a Zero-Length packet should check receiving data length in the DTLN bit of the CFIFOCTR register
after BRDY interruption generating, and should perform a buffer memory clearance in a BCLR bit.
In the case of the data transmitting direction at the time of Hi-Speed communication, a PING packet is
transmitted. Control of a PING packet is the same as that of a bulk transfer. Please refer to Chapter 3.7.1.
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| M66596WG#RB0Z | 制造商:Renesas Electronics 功能描述:Tray 制造商:Renesas 功能描述:0 |
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