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参数资料
| 型号： | M66596WG |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封装： | 0.80 MM PITCH, FBGA-64 |
| 文件页数： | 82/133页 |
| 文件大小： | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 50 of 127
3.1.5
USB data bus resistor control
Figure 3.1 shows a diagram of the connections between the controller and the USB connectors.
For the Peripheral mode, the controller has a built-in pull-up resistor for the D+ signal. “1” should be set for the
DPRPU
bit of the SYSCFG register, then the D+ line is pulled up. The pull-up power supply is AFE33V.
For the Host mode, the controller has a built-in pull-down resistor for the D+ and D- signals. “1” should be set for
the DPRPD bit of the SYSCFG register, then the D+ and D- lines are pulled down.
Also, the controller has a built-in terminal resistor for use when the D+ and D- signals are operating at Hi-Speed,
and a built-in output resistor for Full-Speed operation. The controller automatically switches the built-in resistor
after connection with the PC, by means of reset handshake, suspended state and resume detection. If a disconnection
from the PC is detected, the H/W should be initialized by means of an S/W reset (USBE=0).
If “0” is set for the DPRPU bit of the SYSCFG register in the Peripheral mode, the pull-up resistor (or the terminal
resistor) of the USB data line is disabled, making it possible to notify the host controller of the device disconnection.
M66596
VBUS
USB connector
1
3
2
4 GND
D-
D+
Vbus
DM
DP
RERFIN
5.6K
Impedance control has to be taken into
consideration when designing the D+
and D- lines.
+5V
(at the Host mode)
Figure 3.1 UBS connector connections
3.1.6
Clock supply control
Figure 3.2 shows a block diagram of the controller clock control. Frequency of the input clock for the XIN pin
should be selected using the XTAL bit of the SYSCFG register, while the oscillation buffer is enabled using the XCKE
bit and the clock supply is controlled using the RCKE, PLLC, and SCKE bits. For information on the register control
timing, please refer to 3.1.8, State transition timing.
Auto clock supply
Low-power
control
Input
clock
Oscillation
buffer
XCKE
(bit13)
PLLC, SCKE
(bit11, bit10)
Internal
clock
PLL
Clock control unit
RCKE
(bit12)
Divider
circuit
PCUT
(bit1)
ATCKM
(bit8)
Figure 3.2 Clock control block
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M66596WG#RB0Z | 制造商:Renesas Electronics 功能描述:Tray 制造商:Renesas 功能描述:0 |
| M6668 | 制造商:Tamura Corporation of America 功能描述: |
| M66700P | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
| M66700WP | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
| M66701P | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
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