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参数资料
| 型号： | M66596WG |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封装： | 0.80 MM PITCH, FBGA-64 |
| 文件页数： | 124/133页 |
| 文件大小： | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 88 of 127
3.6.2
Peripheral mode
3.6.2.1 Setup stage
The controller always sends an ACK response in response to a setup packet that is normal with respect to the
controller. The operation of the contoller in the setup stage is noted below.
(1) When a new USB request is received, the controller set following registers:
(2) Set the VALID bit of the INTSTS0 register to “1”.
(3) Set the PID bit of the DCPCTR register to “NAK”.
(4) Set the CCPL bit of the DCPCTR register to “0”.
(5) When a data packet is received right after the SETUP packet, the USB request parameters are stored in the
USBREQ
, USBVAL, USBINDX and USBLENG registers.
Response processing with respect to the controller should always be carried out after first setting “VALID=0”. In
the “VALID=1” state, “PID=BUF” cannot be set, and the data stage cannot be terminated.
Using the function of the VALID bit, the controller is able to interrupt the processing of a request currently being
processed if a new USB request is received during a control transfer, and can send a response in response to the
newest request.
Also, the controller automatically judges the direction bit (bit 8 of the bmRequestType) and the request data
length (wLength) of the USB request that was received, and then distinguishes between control read transfers,
control write transfers, and control write no-data transfers, and controls the stage transition. For a wrong sequence,
the sequence error of the control transfer stage transition interrupt is generated, and the control program is notified.
For information on the stage control of the controller, please refer to Figure 3.17, Control transfer stage transition
diagram.
3.6.2.2 Data stage
Data transfers corresponding to USB requests that have been received should be done using the DCP. Before
accessing the DCP buffer memory, the access direction should be specified using the ISEL bit of the CFIFOSEL
register.
If the data being transferred is larger than the size of the DCP buffer memory, the data transfer should be carried
out using the BRDY interrupt for control write transfers and the BEMP interrupt for control read transfers.
With control write transfers during Hi-Speed operation, the NYET handshake response is carried out based on the
state of the buffer memory. For information on the NYET handshake, please refer to Chapter 3.7.2, NYET
handshake control.
3.6.2.3 Status stage
Control transfers are terminated by setting the CCPL bit to “1” with the PID bit of the DCPCTR register set to
“PID=BUF”.
After the above settings have been entered, the controller automatically executes the status stage in accordance
with the data transfer direction determined at the setup stage. The specific procedure is as follows.
(1) For control read transfers:
The Zero-Length packet is received from the USB host, and the controller sends an ACK response.
(2)
For control write transfers and no-data control transfers:
The controller sends a Zero-Length packet and receives the ACK response from the USB host.
The Zero-Length packet is received from the USB host, and the ACK response is sent.
3.6.2.4 Control transfer auto response function
The controller automatically responds to a normal SET_ADDRESS request. If any of the following errors occur in
the SET_ADDRESS request, a response from the S/W is necessary.
(1)
Any transfer other than a control read transfer:
bmRequestType
≠ "0x00"
(2)
If a request error occurs:
wIndex
≠ "0x00"
(3)
For any transfer other than a no-data control transfer:
wLength
≠ "0x00"
(4)
If a request error occurs:
wValue
> "0x7F"
(5)
Control transfer of a device state error:
DVSQ
= "011(Configured)"
For all requests other than the SET_ADDRESS request, a response is required from the correspondingsoftware.
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