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| 型号： | M66596WG |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封装： | 0.80 MM PITCH, FBGA-64 |
| 文件页数： | 117/133页 |
| 文件大小： | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 82 of 127
3.4.3
DMA transfers (DxFIFO port)
3.4.3.1 An overview of DMA transfers
For pipes 1 to 7, the FIFO port can be accessed using the DMAC.
For DMA transfers, there are two modes that can be selected. One is the cycle steal transfer mode, in which the
DREQ
signal is asserted each time a data element (8 or 16 bits) is transferred. The other is the burst transfer mode,
in which the DREQ signal continues to be asserted until all of the data in the buffer memory has been transferred.
For information regarding the timing, please refer to Chapter 4, Electrical characteristics.
The unit of transfer to the FIFO port (8 or 16 bits) should be selected using the MBW bit of the DxFIFOSEL register,
and the pipe targeted for the DMA transfer should be selected using the CURPIPE bit. The selected pipe should not
be changed during the DMA transfer.
3.4.3.2 Selecting the DMA control signal
The DFORM bit of the DMAxCFG register should be used to select the pin to be used in the DMA transfer.
Table 3.18 shows the DMA control pins of the controller. Figure 3.22 shows the DMA control signal.
Table 3.18 DMA control pins
Register
Pin
Access
method
DREQE
DFORM
DATA BUS DREQ
DACK
RD/WR
ADDR
+CS
DSTB
Note
CP bus 0
0
CPU
-
v
-
CPU access
CPU bus 1
1
0
CPU
v
-
v
-
DMA with CPU bus
CPU bus 2
1
0
1
0
CPU
v
-
DMA with CPU bus
CPU bus 3
1
0
1
CPU
v
-
-
DMA with CPU bus
SPLIT bus 1
1
0
SPLIT
v
-
v
Split bus
SPLIT bus 2
1
0
SPLIT
v
-
Split bus
*1) This access method can be set only in relation to the D0FIFO port. Also, if using the D0FIFO port with this
setting and also using the D1FIFO port, the D1FIFO port should be used with the setting “DFROM=000”.
*2) When this access method is set CS_N pin shoul be held inactive (should be held in the high state) while the
DMAC accsesses to the DxFIFO port.
DREQ
DACK
D15-0
DMA transfer on CPU bus 1
DMA transfer on CPU bus 2
DEND
DREQ
DACK
SD7-0
DMA transfer on split bus 1
DMA transfer on split bus 2
DEND
RD/WR
CS
ADDR
DSTB
Figure 3.22 DMA control pins operation by FIFO port accessing methods
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