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参数资料
| 型号： | M66596WG |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封装： | 0.80 MM PITCH, FBGA-64 |
| 文件页数： | 47/133页 |
| 文件大小： | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 18 of 127
2.3 System control
System configuration control register [SYSCFG]
<Address : 00H>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
XTAL
XCKE
RCKE
PLLC
SCKE
ATCKM
HSE
DCFM DMRPD DPRPU
FSRPC PCUT
USBE
0
-
0
-
0
-
1
0
-
0
-
0
-
0
?
0
-
0
-
0
-
0
-
0
-
?
0
-
0
-
0
-
Bit
Name
Function
S/W
H/W
Note
15-14 XTAL
Clock selection
00: 12 MHz input
01: 24 MHz input
10: 48 MHz input
11: Reserved
R/W
R
13
XCKE
Oscillation buffer enabled
0: Oscillation buffer operation disabled
1: Oscillation buffer operation enabled
R/W
(1)
12
RCKE
Reference clock enabled
0: Reference clock supply stopped
1: Reference clock supply enabled
R/W
R
11
PLLC
PLL operation enabled
0: PLL operation disabled
1: PLL operation enabled
R/W
R
10
SCKE
Internal clock enabled
0: Internal clock supply stopped
1: Internal clock supply enabled
R/W
R
9
Nothing is placed here. It should be fixed at “0”.
8
ATCKM
Auto clock supply function enabled
The clock is supplied from the low-power sleep
state or clock stop state.
0: Auto clock supply function disabled
1: Auto clock supply function enabled
R/W
R
7
HSE
Hi-Speed operation enabled
This enables Hi-Speed operation.
0: Hi-Speed operation disabled (Full-Speed)
1: Hi-Speed operation enabled (detected by
controller)
R/W
R
6
DCFM
0: Peripheral Controller
1: Host Controller
R/W
R
5
DMRPD
D+,D- line resistance control
R/W
R
4
DPRPU
D+,D- line resistance control
For detailed information, refer to Chapter 2.3.4
R/W
R
3
Nothing is placed here. These should be fixed at “0”.
2
FSRPC
Full-Speed receiver enable
0: Full-Speed receiver is controled by H/W
1: Full-Speed receiver enabled by S/W
R/W
R
1
PCUT
Low-power sleep state enabled
0: Normal operation state
1: Low-power sleep state
R/W (1) R/W
(0)
0
USBE
USB block operation enabled
0: USB block operation disabled (S/W Reset)
1: USB block operation enabled
R/W
R
<< Notes >>
*1) The Hi-Speed operation enabled (HSE) bit and Device Controller function (DCFM) should be set before the
internal clock is supplied and .setup DPRPU and DPRPD bit.
*2) When the system returns from the low-power sleep state to the normal operation state, the controller sets
“XCKE = 1”.
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相关代理商/技术参数 |
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|---|---|
| M66596WG#RB0Z | 制造商:Renesas Electronics 功能描述:Tray 制造商:Renesas 功能描述:0 |
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| M66701P | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
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