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参数资料
| 型号： | M66596WG |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封装： | 0.80 MM PITCH, FBGA-64 |
| 文件页数： | 56/133页 |
| 文件大小： | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 27 of 127
CFIFO port selection register [CFIFOSEL]
<Address: 1EH>
D0FIFO port selection register [D0FIFOSEL]
<Address: 24H>
D1FIFO port selection register [D1FIFOSEL]
<Address: 2AH>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RCNT
REW
DCLRM DREQE
MBW
TRENB TRCLR DEZPM
ISEL
CURPIPE
0
-
0
-
0
-
0
-
0
?
0
-
0
-
0
-
0
-
0
?
0
-
0
?
0
-
0
-
0
-
0
Bit
Name
Function
S/W
H/W
Note
15 RCNT
Read Count mode
0: The DTLN bit is cleared when all of the
reception data has been read.
1: The DTLN bit is decremented when the
reception data is read.
R/W
R
14 REW
Buffer pointer rewind
0:
Invalid.
1: The buffer pointer is rewound.
R(0)/W R/W(0) 3.4.2.2
13 DCLRM
This is the Auto Buffer Memory clear
mode accessed after the data for the
specified pipe has been read.
0: The Auto Buffer Clear mode is disabled.
1: The Auto Buffer Clear mode is enabled.
R/W
R
12 DREQE
DREQ signal output enabled
0: Output is disabled.
1: Output is enabled.
R/W
R
11 Nothing is placed here. This should be fixed at “0”.
10 MBW
FIFO port access bit width
0: 8-bit width
1: 16-bit width
R/W
R
9
TRENB
Transaction counter enabled
0: The transaction counter function is invalid.
1: The transaction counter function is valid.
R/W
R
8
TRCLR
Transaction counter clear
0: Invalid
1: The current count is cleared.
R(0)/
W(1)
R
7
DEZPM
Zero-Length Packet Added mode
0: No packet is added.
1: The packet is added.
R/W
R
6
Nothing is placed here. This should be fixed at “0”.
5
ISEL
Access direction of the FIFO port when
DCP is selected
0: This selects reading from the buffer
memory.
1: This selects writing to the buffer memory.
R/W
R
4-3 Nothing is placed here. These should be fixed at “0”.
2-0 CURPIPE
FIFO port access pipe specification
000: DCP / No specification
001: Pipe 1
010: Pipe 2
011: Pipe 3
100: Pipe 4
101: Pipe 5
110: Pipe 6
111: Pipe 7
R/W
R
<<Notes>>
*2) The DCLRM, DREQE, TRENB, TRCLR and DEZPM bits are valid for the D0/D1FIFOSEL registers. The
DCLRM
, TRENB and TRCLR bits are valid when the receiving direction (reading from the buffer memory) has been
set for the pipe specified by the CURPIPE bit. The DEZPM bit is valid when the sending direction (writing to the
buffer memory) has been set for the pipe specified by the CURPIPE bit.
*3) The ISEL bit is valid only when DCP is selected using the CFIFO port selection register. Software should set the
ISEL
bit according to the folowing (a) or (b).
(a) The setting to CURPIPE bit to DCP (“CURPIPE=”0”) and setting to ISEL bit should be done at the same
time.
(b) First software sets CURPIPE bit to DCP (“CURPIPE=”0”), then it sets ISEL bit after 200ns or more.
*4) Once reading from the buffer memory has begun, the access bit width of the FIFO port cannot be changed until
all of the data has been read. Also, the bit width cannot be changed from the 8-bit width to the 16-bit width
while data is being written to the buffer memory.
*5) Specifying"CURPIPE=0"using the D0/D1FIFOSEL register will be interpreted as no pipe having been specified.
Also, the pipe number should not be changed while DREQ output is enabled.
*6) Don’t set the same pipe to CURPIPE of C/D0 / D1FIFOSEL register.
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