- 您现在的位置：买卖IC网 > PDF目录45052 > M66596WG UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 PDF资料下载
参数资料
| 型号： | M66596WG |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封装： | 0.80 MM PITCH, FBGA-64 |
| 文件页数： | 35/133页 |
| 文件大小： | 1611K |
| 代理商： | M66596WG |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页当前第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页
M66596FP/WG
rev .1.00
2006.3.14
page 11 of 127
1.7.4
USB data transfers
The controller is capable of all types of transfers: USB communication control transfers, bulk transfers, and
interrupt transfers, as well as isochronous data transfers. The pipes noted below can be used with data transfers
for various types of communication.
(1) Dedicated control transfer pipe(Default Control Pipe(DCP))
(2) Two dedicated interrupt transfer pipes(Pipe6,7)
(3) Three dedicated bulk transfer pipes(Pipe3, 4, 5)
(4) Two pipes for which bulk transfers or isochronous transfers can be selected(Pipe1, 2)
The settings necessary for USB transfers, such as the transfer type, end point number, and maximum packet
size, should be set for each pipe, in conjunction with the user system.
Also, the controller has a built-in 5 kB buffer memory. For a dedicated bulk transfer pipe and the pipes for
which bulk transfers or isochronous transfers can be selected, settings such as the buffer memory assignment
and buffer operation mode which are based on the user system should be entered. The buffer operation mode
setting can be set to enable high-speed data transfers with few interrupts, using the double-buffer configuration
and data packet continuous transfer function.
Access to the buffer memory from the control CPU of the user’s system and the DMA controller is done
through the three FIFO port registers.
1.7.5
DMA interface
The DMA (Direct Memory Access) interface consists of data transfers between the user system and the
controller using the DxFIFO port, and is a type of data transfer in which the CPU is not involved. The controller
is equipped with a 2-channel DMA interface and has the following functions.
(1) A transfer end notification function using the Transfer End signal (DEND signal)
(2) An auto-clear function activated when a Zero-Length packet is received
(3) A “send addition” function used to send a Zero-Length packet based on input of the Transfer End signal
(DEND signal)
(4) A transfer end function using a transaction counter function
The controller supports the two types of DMA interfaces noted below.
(5) Cycle steal transfer
With this type of transfer, the DREQ pin is repeatedly asserted and negated each time a data transfer (1 byte /
1 word) is carried out.
(6) Burst transfer
With this type of transfer, the DREQ pin remains asserted for the pipe buffer area assigned to the pertinent
FIFO port, or until the transfer is ended by the DEND signal, without ever being negated.
Also, the following can be selected as the DMA interface handshake signal (pin): CS_N, RD_N, or WR_N, or
DACK_N. With DMA transfers using a split bus, high-speed DMA transfers are possible by changing the data
setup timing, by operating the OBUS bit of the DMAxCFG register.
1.7.6
SOF pulse output function
An SOF pulse output function is provided that notifies the system of the timing at which SOF packets are
transmited or received.
In the Host mode, when the controller transmits a SOF packet, the controller outputs pulses to an SOF_N pin.
In the Peripheral mode, when the controller recives SOF packet, the controller outputs pulse. And the
controller outputs pulses at fairly regular intervals, using an SOF interpolation timer, even if an SOF packet is
damaged. In the Peripheral mode, it is also possible to output the pulse only when an SOF packet is damaged.
相关PDF资料 |
PDF描述 |
|---|---|
| M6XXLFXI | OTHER CLOCK GENERATOR, QCC16 |
| M300LFXIT | 50 MHz, OTHER CLOCK GENERATOR, QCC16 |
| M74HC00C1R | HC/UH SERIES, QUAD 2-INPUT NAND GATE, PQCC20 |
| M74HC157B1N | HC/UH SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDIP16 |
| M74HC158C1 | HC/UH SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PQCC20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M66596WG#RB0Z | 制造商:Renesas Electronics 功能描述:Tray 制造商:Renesas 功能描述:0 |
| M6668 | 制造商:Tamura Corporation of America 功能描述: |
| M66700P | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
| M66700WP | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
| M66701P | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
发布紧急采购，3分钟左右您将得到回复。