参数资料
型号: M66596WG
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封装: 0.80 MM PITCH, FBGA-64
文件页数: 23/133页
文件大小: 1611K
代理商: M66596WG
M66596FP/WG
rev .1.00
2006.3.14
page 117 of 127
4.9.4
DMA access timing(cycle steal transfer, when a multiplex bus is set)
4.9.4.1 DMA cycle steal transfer write timing (CPU multiplex bus setting: DFORM=000)
tdis (CTRLH - Dreq)
twh (Dreq)
18
20
ten (CTRL - Dreq) 19
DREQi_N
(i=0,1)
tsu (DEND)
th (DEND)
45
46
DENDi_N
(i=0,1)
DENDi_N determination
AD6-AD1 /
D15-D0
CS_N
WR1_N,
WR0_N
Note 4-1
Address
determination
ALE
tsu (A - ALE)
32
th (A - ALE)
35
tsu (D)
43
th (D) 44
tw (ALE)
36
37
tw (CTRL) 39
trec (ALE)
38
Note 4-3
tdwr (ALE - CTRL)
Address
determination
Data determination
4.9.4.2 DMA cycle steal transfer read timing (CPU multiplex bus setting: DFORM=000)
DREQi_N
(i=0,1)
tdis (CTRL - Dreq)
17
twh (Dreq) 20
ten (CTRL - Dreq)
19
32
A6-A1 /
D15-A0
CS_N
RD_N
Note 4-2
Address
determination
ALE
tsu (A - ALE) th (A - ALE)
35
tw (ALE)
36
tdwr (ALE - CTRL)
37
ten (CTRL - D)
5
ta (CTRL - D)
3
tv (CTRL - D)
4
tdis (CTRL - D) 6
twr (CTRL) 42
trec (ALE) 38
Note 4-3
DENDi _N
(i=0,1)
ta (CTRL - DendV) 11
tv (CTRL - DendV)
12
Data determination
Address
determination
DENDi_N determination
Note 4-4
Note 4-1: The control signal when writing data is a combination of CS_N, WR0_N, and WR1_N.
Note 4-2: The control signal when reading data is a combination of CS_N and RD_N.
Note 4-3: RD_N, WR0_N and WR1_N should not be timed to fall at the same time that CS_N is rising. Similarly, CS_N
should not be timed to fall (or rise) at the same timing that RD_N or WR0_N and WR1_N are rising. In the
instances noted above, an interval of at least 10 ns must be left open.
Note 4-4: When the receipt data is one byte, the DEND determined time is "(24)td(DREQ-DendV)".
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