参数资料
型号: M66596WG
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封装: 0.80 MM PITCH, FBGA-64
文件页数: 132/133页
文件大小: 1611K
代理商: M66596WG
M66596FP/WG
rev .1.00
2006.3.14
page 96 of 127
3.9.5
Isochronous transfer transmission buffer flush
In the Peripheral mode if a (u) SOF packet is received without an IN token having been received in the interval
frame during isochronous data transmission, the controller operates as a IN token had been corrupted, and clears
the buffer for which transmission is enabled, putting that buffer in the writing enabled state.
If a double buffer is being used at that time and writing has been finished to both buffers, the buffer memory that
was cleared is seen as the data having been sent at the same interval frame, and transmission is enabled for the
other buffer memory.
The timing at which the operation of the buffer flush function begins varies depending on the value set for the
IITV bit.
(1)
If IITV=0
The buffer flush operation starts from the next frame after the pipe becomes valid.
(2)
In any case other than IITV=0
The buffer flush operation is carried out subsequent to the first normal transaction.
Figure 3.27 shows an example of the buffer flush function of the controller. When an unanticipated token prior to
the interval frame is received, the controller sends the written data or a Zero-Length packet are sent in accordance
with buffer state.
Transmission enabled state
Writing in
progress
Buffer A
Buffer B
Writing completed
Empty state
Writing in
progress
Writing completed
Writing in
progress
Writing completed
Transmission enabled state
Figure 3.27 Example of buffer flush function operation
Figure 3.28 shows an example of the controller generating an interval error. There are five types of interval errors,
as noted below. The interval error is generated at the timing indicated by
in the illustration, and the buffer flush
function is activated.
If the interval error occurs during an IN transfer, the buffer flush function is activated, and if it occurs during an
OUT transfer an NRDY interrupt is generated.
The OVRN bit should be used to distinguish between NRDY interrupts such as received packet errors and overrun
errors.
In response to tokens that are shaded in the illustration, responses occur based on the buffer memory status.
(1)
IN direction
(a) If the buffer is in the transmission enabled state, the data is transferred as a normal response .
(b) If the buffer is in the transmission disabled state, a Zero-Length packet is sent and an underrun error
occurs.
(2)
OUT direction
(a) If the buffer is in the reception enabled state, the data is received as a normal response.
(b) If the buffer is in the reception disabled state, the data is decarded and an overrun error occurs.
Token
Normal transfer
Token
Token damaged
Token
Token delayed
Token
Frame misaligned
Token
Packet inserted
Token
1
SOF
Frame misaligned
Figure 3.28 Example of interval error being generated when “IITV=1”
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