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参数资料
| 型号： | M66596WG |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封装： | 0.80 MM PITCH, FBGA-64 |
| 文件页数： | 9/133页 |
| 文件大小： | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 104 of 127
4.7 Switching characteristics (VIF = 2.7~3.6V, or 1.6~2.0V)
Rated value
Symbol
Item
Measurement
conditions /
other
Min.
Typ.
Max.
Unit
Ref.
no.
ta (A)
Address access time
CL=50 pF
40
ns
1
tv (A)
Time that data is valid after address
CL=10 pF
2
ns
2
ta (CTRL - D)
Time that data can be accessed after
control
CL=50 pF
30
ns
3
tv (CTRL - D)
Time that data is valid after control
CL=10 pF
2
ns
4
ten (CTRL - D)
Time that data output is enabled after
control
2
ns
5
tdis (CTRL - D)
Time that data output is disabled after
control
CL=50 pF
30
ns
6
ta (CTRL - DV)
Time that data can be accessed after
control when split bus (DMA Interface)
Obus=0
CL=30 pF
30
ns
9
tv (CTRL – DV)
Time that data can is valid after control
when split bus (DMA Interface) Obus=0
CL=10 pF
2
ns
10
ta (CTRL - DendV)
Time that DEND output can be accessed
after control when split bus (DMA
Interface) Obus=0
CL=30 pF
30
ns
11
tv (CTRL - DendV)
Time that DEND output is valid after
control when CPU bus and split bus
(DMA Interface) Obus=0
CL=10 pF
2
ns
12
ta (CTRL - Dend)
Time that DEND output can be accessed
after control when split bus (DMA
Interface) Obus=1
CL=30 pF
30
ns
13
tv (CTRL – Dend)
Time that DEND output is valid after
control when CPU bus and split bus
(DMA Interface) Obus=1
CL=10 pF
2
ns
14
ten (CTRL – Dend)
Time that DEND output is enabled after
control when CPU bus and split bus
(DMA Interface) Obus=1
2
ns
15
tdis (CTRL-Dend)
Time that DEND output is disabled after
control when CPU bus and split bus
(DMA Interface) Obus=1
CL=30 pF
30
ns
16
tdis (CTRL – Dreq)
Time that DREQ is disabled after control
70
ns
17
tdis (CTRLH –Dreq)
Time that DREQ is disabled after control
70
ns
18
ten (CTRL – Dreq)
Time that DREQ is enabled after control
30
ns
19
twh (Dreq)
DREQ output "H" pulse width
20
50
ns
20
td (CTRL - INT)
INT output negated delay time
250
ns
21
twh (INT)
INT output “H” pulse width
650
ns
22
td (DREQ - DV)
Data access after DREQ begins to be
asserted when split bus (DMA Interface)
Obus=0
0
ns
23
td (DREQ - DendV)
Time that DEND can be accessed after
DREQ begins to be asserted when split
bus (DMA Interface) Obus=0
0
ns
24
Key
ta: Access time, tv: Valid time, ten: Output enabled time, tdis: Output disabled time, td: propagation delay
(A): Address, (D): Data, (Dend): DEND, (CTRL): Control, (V): Obus=0
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