- 您现在的位置：买卖IC网 > PDF目录45052 > M66596WG UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 PDF资料下载
参数资料
| 型号： | M66596WG |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封装： | 0.80 MM PITCH, FBGA-64 |
| 文件页数： | 92/133页 |
| 文件大小： | 1611K |
| 代理商： | M66596WG |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页当前第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页
M66596FP/WG
rev .1.00
2006.3.14
page 59 of 127
3.1.8.6 Starting the internal clock
(From the clock stop state to the normal operating state : with “ATCKM=0”)
The timing diagram from the clock stop state to the normal operation is shown in Figure 3.10. The diagram is in
the case of the auto clock supply function is disabled ("ATCKM=0"). When the auto clock supply function is disabled,
register control is performed by software. Softwear should operate registers according to the following sequence.
(1) The controller detects the resume on a USB bus or attachment of the USB cable, and the INT_N pin is
asserted.
(2) When the resume is detected, the controller automatically enables the oscillation buffer. "XCKE=1(H/W)"
When attachment of USB cable is detected, software enables the oscillation buffer. "XCKE=1(S/W)"
(3) The software waits for oscillation to stabilize. *1)
(The oscillation stabilization time varies depending
on the oscillator.)
(4) The software enables the reference clock suppliance
"RCKE=1", "PLLC=1"
and the PLL operation
(5) The software waits for the PLL to lock.
(A waiting time of at least 8.3 us is necessary.)
(6) The software enables the internal clock suppliance.
"SCKE=1"
(7) Software performs depending on the interrupt factor, resume or attachment.
*1) When it returns with a USB bus reset signal from the suspend state, it is necessary to return to the normal
operation state less than 3ms and the controller start a reset handshake protocol. For this reason, when an
auto clock supply function is disabled, it is necessary to perform a processings to oscillation stability waiting
and clock supply by software within 3ms.
XCKE
Resume :H/W
VBUS chage :S/W
RCKE(H/W)
PLLC(H/W)
SCKE(H/W)
(3)
Clock stop
recovery
INT_N
Event
(1),(2)
(6)
(5) min 8.3us
(4)
Figure 3.10 Recovery control timing from the clock stop state with “ATCKM=0”
相关PDF资料 |
PDF描述 |
|---|---|
| M6XXLFXI | OTHER CLOCK GENERATOR, QCC16 |
| M300LFXIT | 50 MHz, OTHER CLOCK GENERATOR, QCC16 |
| M74HC00C1R | HC/UH SERIES, QUAD 2-INPUT NAND GATE, PQCC20 |
| M74HC157B1N | HC/UH SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDIP16 |
| M74HC158C1 | HC/UH SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PQCC20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M66596WG#RB0Z | 制造商:Renesas Electronics 功能描述:Tray 制造商:Renesas 功能描述:0 |
| M6668 | 制造商:Tamura Corporation of America 功能描述: |
| M66700P | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
| M66700WP | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
| M66701P | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
发布紧急采购，3分钟左右您将得到回复。