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参数资料
| 型号： | M66596WG |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封装： | 0.80 MM PITCH, FBGA-64 |
| 文件页数： | 74/133页 |
| 文件大小： | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 43 of 127
DCP control register [DCPCTR]
<Address: 60H>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BSTS SUREQ
SQCLR SQSET SQMON
CCPL
PID
0
-
0
-
0
?
0
-
0
-
0
1
-
1
?
0
Bit
Name
Function
S/W
H/W
Note
15
BSTS
Buffer Status
0: Buffer access is disabled.
1: Buffer access is enabled.
R
W
3.4.1.1
14
SUREQ
Request to transmit SETUP packet
A SETUP packet is transmitted by setting this
bit to 1.
0: Invalid
1: transmit SETUP packet
R/W(1) R/W(0) 3.6.1
14-9 Nothing is placed here. These should be fixed at “0”.
8
SQCLR
Toggle Bit Clear
0: Invalid
1: Specifies DATA0
R(0)/
W(1)
R
7
SQSET
Toggle Bit Set
0: Invalid
1: Specifies DATA1
R(0)/
W(1)
R
6
SQMON
Toggle Bit Confirm
0: DATA0
1: DATA1
R
W
5-3 Nothing is placed here. These should be fixed at “0”.
2
CCPL
Control Transfer End enabled
0: Invalid
1: The control transfer is ended.
R(0)/
W(1)
R/W(0) 3.6.2
1-0 PID
Response PID
00: NAK response
01: BUF response (in keeping with the buffer
state)
10: STALL response
11: STALL response
R/W
<<Notes>>
*5) The direction of buffer access, writing or reading, is depend on setting of ISEL bit.
*6) In the peripheral mode the CCPL bit is cleared to “0” right after the SETUP token has been received.
In the host mode this bit should be set “CCPL=0”(not use).
*7) If the SQSET bits and the SQCLR bits of the DCPCTR register and the PIPExCTR registers are being changed
in succession (the PID sequence toggle bits of multiple pipes are being changed in succession), an access cycle of
at least 200 ns is required.
*8) The SQCLR bit and SQSET bit should not both be set to “1” at the same time. Before operating either bit,
“PID=NAK” should be set.
*9) In the Peripheral mode the SQMON bit is initialized to “1” by the controller right after the SETUP token of the
control transfer has been received.
*10) In the peripheral mode the PID bit is cleared to “00” right after the SETUP token has been received. And at the
time of occurring of a transmission error etc., PID bits are set up by the controller and transmission is ended.
*11) When SUREQ bit is set to 1, it is set to 0 by H/W after SETUP transaction sending out.
While the SUREQ bit is 1, do not write in USBREQ, USBVAL, USBINDX, and a USBLENG register.
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相关代理商/技术参数 |
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