参数资料
型号: M66596WG
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封装: 0.80 MM PITCH, FBGA-64
文件页数: 18/133页
文件大小: 1611K
代理商: M66596WG
M66596FP/WG
rev .1.00
2006.3.14
page 112 of 127
4.9.3.6 DMA cycle steal transfer write timing (CPU separate bus setting: DFORM=000)
50
tsud (A)
thd (A)
51
tw (CTRL) 39
tsu (D)
th (D)
43
44
A6-A1
CS_N
WR0_N,
WR1_N
D15-D0
tdis (CTRLH - Dreq)
twh (Dreq)
18
20
ten (CTRL - Dreq) 19
DREQi_N
(i=0,1)
Note 3-5
tsu (DEND)
th (DEND)
45
46
DENDi _N
(i=0,1)
Note 3-7
Data determination
DENDi_N determination
Address determination
Note 3-1
4.9.3.7 DMA cycle steal transfer read timing (CPU separate bus setting: DFORM=000)
31
tsur (A)
thr (A)
34
twr (CTRL)
42
tv (CTRL - D)
tdis (CTRL - D)
5
ten (CTRL - D)
4
6
ta (CTRL - D)
3
ta (A)
1
Note 3-6
2
tv (A)
tdis (CTRL - Dreq)
17
twh (Dreq)
20
ten (CTRL - Dreq)
19
Note 3-7
ta (CTRL - DendV)
11
tv (CTRL - DendV)
12
Data determination
CS_N
RD_N
D15-D0
DREQi_N
(i=0,1)
DENDi _N
(i=0,1)
A6-A1
Address determination
Note 3-1
DENDi_N determination
Note 3-9
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