参数资料
型号: M66596WG
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封装: 0.80 MM PITCH, FBGA-64
文件页数: 78/133页
文件大小: 1611K
代理商: M66596WG
M66596FP/WG
rev .1.00
2006.3.14
page 47 of 127
Pipe timing control register [PIPEPERI]
<Address: 6CH>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IFIS
IITV
?
0
-
0
?
0
-
0
-
0
-
0
Bit
Name
Function
S/W
H/W
Note
15-13 Nothing is placed here. These should be fixed at “0”.
12
IFIS
Isochronous IN buffer flush
0: The buffer is not flushed.
1: The buffer is flushed.
R/W
R
11-3 Nothing is placed here. These should be fixed at “0”.
2-0 IITV
Interval error detection spacing
Specifies the interval timing as
IITV-th power
of
2.
R/W
R
<<Note>>
*11) In the peripheral mode the IITV bit is valid only when isochronous transfer is selected. It can be set only when
PIPE1-2 are selected.
For OUT-direction: An interval error occurs upon a NRDY interrupt caused by a token not having been issued.
For IN-direction: When the controller doesn't receive IN-token until the time indicated by IITV bit, it detects an
interval error and flushs the buffer.
In the host mode the IITV bit is valid only when isochronous and interrupt transfer is selected. The IITV bit
controls the interval of a transaction.
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