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参数资料
| 型号： | M66596WG |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封装： | 0.80 MM PITCH, FBGA-64 |
| 文件页数： | 113/133页 |
| 文件大小： | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 78 of 127
3.4.1.3 Buffer areas
Table 3.15 shows the FIFO buffer memory map of the controller. The buffer memory has special fixed areas to
which pipes are assigned in advance, and user areas that can be set by the user. The buffer for the DCP is a
special fixed area that is used both for control read transfers and control write transfers. The PIPE6-7 area is
assigned in advance, but the area for pipes that are not being used can be assigned to PIPE1-5 as a user area.
The settings should ensure that the areas of the various pipes do not overlap. Also, the buffer size should not be
specified using a value that is less than the maximum packet size.
Table 3.15 Buffer memory map
Buffer memory no.
Buffer size
Pipe setting
Note
0 – 3
256 bytes
DCP special fixed area
Single buffer, continuous transfers
enabled
4
64 bytes
Fixed area for PIPE6
Single buffer
5
64 bytes
Fixed area for PIPE7
Single buffer
6 – 4F
4736 bytes
PIPE1-5 user area
Double buffer can be set, continuous
transfers enabled
3.4.1.4 Auto Buffer Clear mode function
With this controller, all of the received data packets are discard if the ACLRM bit of the PIPExCTR register is
set to “1”. If a normal data packet has been received, however, the ACK response is returned to the host
controller. This function can be set only in the buffer memory reading direction.
Also, if the ACLRM bit is set to “1” and then to “0”, the buffer memory of the pertinent pipe can be cleared
regardless of the access direction. An access cycle of at least 100 ns is required between “ACLRM=1” and
“ACLRM=0”.
3.4.1.5 Buffer memory specifications (single / double setting)
Either a single or double buffer can be selected for PIPE1-5, using the DBLB bit of the PIPExCFG register. The
double buffer is a function that assigns two memory areas specified with the BUFSIZE bit of the PIPEBUF
register to the same pipe. Figure 3.20 shows an example of buffer memory settings for the controller.
64 Byte
128 Byte
BUFSIZE=0,
DBLB=0
BUFIZE=0,
DBLB=1
BUFSIZE=1,
DBLB=0
Buffer memory
PIPEBUF reg
Figure 3.20 Example of buffer memory settings
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