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参数资料
| 型号： | M66596WG |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封装： | 0.80 MM PITCH, FBGA-64 |
| 文件页数： | 65/133页 |
| 文件大小： | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 35 of 127
2.9 Interrupt statuses
Interrupt status register 0[INTSTS0]
<Address: 40H>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VBINT
RESM
SOFR
DVST
CTRT
BEMP
NRDY
BRDY VBSTS
DVSQ
VALID
CTSQ
0
-
0
-
0
-
0
1
0
-
0
-
0
-
0
-
0
?
-
?
0
1
0
-
0
-
0
-
0
-
0
Bit
Name
Function
S/W
H/W
Note
15 VBINT
VBUS interrupt status
0: VBUS interrupts not issued
1: VBUS interrupts issued
R/W
W
14 RESM
Resume interrupt status
0: Resume interrupts not issued
1: Resume interrupts issued
R/W
W
13 SOFR
Frame number refresh interrupt status
0: SOF interrupts not issued
1: SOF interrupts issued
R/W(0)
W
12 DVST
Device state transition interrupt status
0: Device state transition interrupts not issued
1: Device state transition interrupts issued
R/W(0)
W
11 CTRT
Control transfer stage transition interrupt
status
0: Control transfer stage transition interrupts
not issued
1: Control transfer stage transition interrupts
issued
R/W(0)
W
10 BEMP
Buffer Empty interrupt status
0: BEMP interrupts not issued
1: BEMP interrupts issued
R
W
9
NRDY
Buffer Not Ready interrupt status
0: NRDY interrupts not issued
1: NRDY interrupts issued
R
W
8
BRDY
Buffer Ready interrupt status
0: BRDY interrupts not issued
1: BRDY interrupts issued
R
W
7
VBSTS
VBUS input status
0: VBUS pin is “L” level
1: VBUS pin is “H” level
R
W
6-4 DVSQ
Device state
000: Powered state
001: Default state
010: Address state
011: Configured state
1xx: Suspended state
R
W
3
VALID
Setup packet reception
0: Not detected
1: Setup packet reception
R/W(0)
W
2-0 CTSQ
Control transfer stage
000: Idle or setup stage
001: Control read data stage
010: Control read status stage
011: Control write data stage
100: Control write status stage
101: Control write (NoData) status stage
110: Control transfer sequence error
111: Reserved
R
W
<<Note>>
*1) The BEMP, BRDY and NRDY bits are cleared when all of the factors for each pipe on correcponding registers
have been eliminated, i.e. BEMPSTS, BRDYSTS and NRDYSTS.
*2) The VBUS input status based on the VBSTS bit requires that chattering be eliminated using software.
*3) If multiple factors are being generated among the VBINT, RESM, SOFR, DVST, and CTRT bits, an access cycle
of at least 100 ns is required in order to clear the bits in succession, rather than simultaneously.
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