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| 型号： | M66596WG |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封装： | 0.80 MM PITCH, FBGA-64 |
| 文件页数： | 85/133页 |
| 文件大小： | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 53 of 127
3.1.7.3 Low-power sleep state
The low-power sleep state is set by setting “1” for the PCUT bit of the SYSCFG register. For information on the
sequence in which settings are entered for the low-power sleep state, please refer to Chapter 3.1.8.2 , and for
information on register control timing, please refer to the timing diagram noted later (Figure 3.6 Low-power control
timing diagram).
In the low-power sleep state, of the registers set by software, only registers other than those noted below are
initialized. After returning to the normal operating state, the settings must be re-entered using software. Table 3.5
shows the registers that are not initialized when the controller is in the low-power sleep state.
Table 3.5 Registers that are not initialized in the low-power sleep state
Register
Bit
Description
XTAL
This is retained as system information.
ATCKM
This is retained as system information.
HSE
This is retained as system information.
DCFM
This is retained as system information.
DMRPD
This is retained as system information.
DPRPU
This is retained as system information.
FSRPC
This is retained as system information.
SYSCFG
USBE
This is retained as system information.
PINCFG
LDRV
The state of the output pin drive current settings is retained.
DMAxCFG
DREQA
The polarity of the DREQ0_N pin and the DREQ1_N pin are retained.
VBSE / VBINT
When "VBSE=1", if there was any change to the VBUS signal in the low-power
sleep state, the INT_N pin is asserted and notification is made to the CPU.
INTENB0/
INTSTS0
RSME / RESM
When "RSME=1", if there was any change to the USB data bus in the low-power
sleep state, the INT_N pin is asserted and notification is made to the CPU.
INTENB1/
INTSTS1
BCHGE / BCHG
When "BCHGE=1", if there was any change to the USB data bus in the low-power
sleep state, the INT_N pin is asserted and notification is made to the CPU.
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