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| 型号： | M66596WG |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封装： | 0.80 MM PITCH, FBGA-64 |
| 文件页数： | 121/133页 |
| 文件大小： | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 86 of 127
3.5 Data setup timing
This section describes the OBUS bit used to select the timing of split bus.. When there is no description, both a
Host and Peripheral are the same operation.
With this controller, the timing of the SD0-7 and DEND pin can be changed as shown in
Table 3.22, using the OBUS bit
of the DMAxCFG
register The OBUS bit is a function that is valid only for DMA transfers using a split bus. When
using the CPU bus for DMA transfers, the setting of the OBUS bit is ignored.
Table 3.22 Differences in operation based on the value set for the OBUS bit
Direction
OBUS
bit setting
Operation
0
The SD0-7 and DEND signals are output on an ongoing basis, regardless of the control
signal *1)
The next data is output when the control signal is negated.
This assures data setup time for the DMAC and enables high-performance DMA transfers.
Reading
1
The SD0-7 and DEND signals are output after the control signal has been asserted.
The SD0-7 and DEND signals go to the Hi-Z state when the control signal is negated.
0
The SD0-7 and DEND signals can be input on an ongoing basis, regardless of the DACKx_N
signal.
The DMAC can output the next data before the DACKx_N signal is asserted.
This assures data setup time for the controller and enables high-performance DMA transfers.
Writing
1
The SD0-7 and DEND signals can be input only if the DACKx_N signal is asserted.
The SD0-7 and DEND signals are ignored if the DACKx_N signal is negated.
*1) “Control signal” refers to the DACKx_N signal if the DFORM[9-7] of the DMAxCFG register is “100”.
If the DFORM[9-7] is ”110”, it refers to both DACK0_N and DSTRB0_N. In this case, “assertion of the control
signal” means the state in which either DACK0_N or DSTRB0_N is asserted.
If “OBUS=0” is set in the reading direction, the SD0-7 and DEND signals are output on an ongoing basis, so please
be aware that sharing the bus with another device can cause the signals to collide.
If “OBUS=0” is set in the writing direction, the SD0-7 and DEND signals can be input on an ongoing basis, so the
user should make sure that the signals are not set to an intermediate potential.
Figure 3.25 shows a schematic diagram of the data setup timing based on the OBUS bit.
OBUS=1: Normal mode
OBUS=0: High-speed mode
DREQ
DACK
SD7-0
DEND
Figure 3.25 Schematic diagram of data setup timing
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