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参数资料
| 型号： | M66596WG |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封装： | 0.80 MM PITCH, FBGA-64 |
| 文件页数： | 97/133页 |
| 文件大小： | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 64 of 127
Table 3.9 Conditions under which a BRDY interrupt is generated
Access
direction
Transfer
direction
Pipe
BFRE
DBLB
Conditions under which a BRDY interrupt is generated
DCP
-
(1) or (2) bellow;
(1) Short packet reception including , Zero-Length packet reception
(2) Buffer is full by reception
0
(1) (2) or (3) bellow;
(1) Short packet reception including , Zero-Length packet reception
(2) Buffer is full by reception *1)
(3) Transaction Counter End when buffer is not full
1
(1), (2), (3) or (4) bellow
(1) One of (a) to (c) conditions is occur when both buffers are waiting
for receiption
(a) a short packet reception including a Zero-Length packet reception
(b) One buffer of two is full by reception
(c) Transaction Counter End when a buffer is not full
(2) Reading is complete of a buffer, when both buffer are waiting for
reading
(3) Software set “BCLR=1” to clear a buffer, when both buffer are
waiting for reading
(4) Software set “TGL=1”, when SIE side buffer has a data In the
continuous transfer mode.
Reading
Receive
1-7
1
Don’t
Care
(1), (2) or (3) bellow
(1) Zero-Length packet reception
(2) After a short packet reception, reading data of the packet is
complete.
(3) After Transaction Counter End reading data of the last packet is
complete,.
DCP
-
Doesn’t take place
1-7
0
(1), (2), (3) or (4) bellow;
(1) Software set direction of transfer to transmitting
(2) Packet transmission is completed
(3) Software set “ACLRM=1”, when there are data waiting to
transmitted
(4) Software set “SCLR=1”, when there are data waiting to transmitte
0
1
(1), (2), (3), (4) or (5) bellow;
(1) Software set direction of transfer to transmitting
(2) Data is enabled to be transmitted, when there are no buffer
waiting to be transmitted.
(3) Data is enabled to be transmitted,, when there are no buffer
waiting to be transmitted.
(a) A buffer is full by writing
(b) Software set “BVAL=1” to enable the buffer is ready to tarnsmit
(c) DMAC asserts DEND signal to make a buffer be ready to transmit
(4) Software set “ACLRM=1”, when there are data waiting to
transmitted
(5) Software set “SCLR=1”, when there are data waiting to transmitte
Writing
Transmit
1-7
1
Don’t
Care
Doesn’t take place
*1) Buffer full shows the following cases.
- In continuous mode ("CBTMD=1" setup), the data of buffer size is received.
- In not continuous mode ("CNTMD=0") , the data of the Max packet size is received.
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