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参数资料
型号： M66596WG
元件分类： 总线控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封装： 0.80 MM PITCH, FBGA-64
文件页数： 60/133页
文件大小： 1611K
代理商： M66596WG
M66596FP/WG
rev .1.00
2006.3.14
page 30 of 127
2.7 Interrupts enabled
Interrupts enabled register 0[INTENB0]
<Address: 30H>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VBSE
RSME
SOFE
DVSE
CTRE BEMPE NRDYE BRDYE URST
SADR
SCFG
SUSP
WDST
RDST
CMPL
SERR
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
Bit
Name
Function
S/W
H/W
Note
15
VBSE
VBUS interrupts enabled
0: Interrupt output disabled
1: Interrupt output enabled
R/W
R
2.7.1
2.7.8
3.2.9
14
RSME
Resume interrupts enabled
0: Interrupt output disabled
1: Interrupt output enabled
R/W
R
2.7.1
2.7.8
3.2.10
13
SOFE
Frame number refresh interrupts enabled
0: Interrupt output disabled
1: Interrupt output enabled
R/W
R
2.7.1
3.2.8
12
DVSE
Device state transition interrupts enabled
0: Interrupt output disabled
1: Interrupt output enabled
R/W
R
2.7.1
2.7.2
3.2.6
11
CTRE
Control transfer stage t
ransition interrupts enabled
0: Interrupt output disabled
1: Interrupt output enabled
R/W
R
2.7.1
2.7.3
3.2.7
10
BEMPE
Buffer Empty interrupts enabled
0: Interrupt output disabled
1: Interrupt output enabled
R/W
R
2.7.1
3.2.5
9
NRDYE
Buffer Not Ready response interrupts enabled
0: Interrupt output disabled
1: Interrupt output enabled
R/W
R
2.7.1
3.2.4
8
BRDYE
Buffer Ready interrupts enabled
0: Interrupt output disabled
1: Interrupt output enabled
R/W
R
2.7.1
3.2.3
7
URST
Default state transition notifications enabled
0: DVST interrupt disabled at transition to
default state
1: DVST interrupt enabled at transition to
default state
R/W
R
2.7.2
3.2.6
6
SADR
Address state transition notifications enabled
0: DVST interrupt disabled at transition to
address state
1: DVST interrupt enabled at transition to
address state
R/W
R
2.7.2
3.2.6
5
SCFG
Configuration state transition notifications
enabled
0: DVST interrupt disabled at transition to
configuration state
1: DVST interrupt enabled at transition to
configuration state
R/W
R
2.7.2
3.2.6
4
SUSP
Suspend state transition notifications enabled
0: DVST interrupt disabled. at transition to
suspend state
1: DVST interrupt enabled at transition to
suspend state
R/W
R
2.7.2
3.2.6
3
WDST
Control write transfer status stage transition
notifications enabled
0: CTST interrupt disabled at transition to
status stage of control write transfer
1: CTST interrupt enabled at transition to
status stage of control write transfer
R/W
R
2.7.3
3.2.7
2
RDST
Control read transfer status stage transition
notifications enabled
0: CTST interrupt disabled at transition to
status stage of control read transfer
1: CTST interrupt enabled at transition to
status stage of control read transfer
R/W
R
2.7.3
3.2.7
1
CMPL
Control transfer end notifications enabled
0: CTST interrupt are disabled at end of
control transfer
1: CTST interrupt enabled at end of control
transfer
R/W
R
2.7.3
3.2.7
0
SERR
Control transfer sequence error notifications
enabled
0: CTST interrupt disabled at detection of
control transfer sequence error
1: CTST interrupt enabled at detection of
control transfer sequence error
R/W
R
2.7.3
3.2.7
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