- 您现在的位置：买卖IC网 > PDF目录45052 > M66596WG UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 PDF资料下载
参数资料
| 型号： | M66596WG |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封装： | 0.80 MM PITCH, FBGA-64 |
| 文件页数： | 127/133页 |
| 文件大小： | 1611K |
| 代理商： | M66596WG |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页当前第127页第128页第129页第130页第131页第132页第133页
M66596FP/WG
rev .1.00
2006.3.14
page 91 of 127
3.8.1
Interval counter in the Host mode
3.8.1.1 Overview
Set the interval of a transaction as the IITV bit of PIPEPERI at the Interrupt transfer. This controller sends out the
token of Interrupt transfer according to the IITV bit.
3.8.1.2 Initialization of a counter
The conditions on which this controller initializes an interval counter are as follows.
(1) H/W reset
IITV
bit is initialized.
(2) S/W reset
IITV
bit is initialized.
(3) The return from Low-power sleep state
An IITV bit is initialized.
(4) Buffer memory initialization by ACLRM
A count is initialized although an IITV bit is not initialized. By setting an ACLRM bit to 0, the setting value of
IITV
is counted from the beginning.
In the following cases, an interval counter is not initialized.
(1) USB bus reset, USB suspensd
An IITV bit is not initialized. By setting a UACT bit to 1, a count is started from the value before considering
as USB bus reset or a USB suspend state.
3.8.1.3 When a token is not transmitted
When as follows, a token is not transmitted even if it is the transmitting timing of a token. In such a case,
execution of a transaction is tried at the next interval.
(1) When PID is set as NAK or STALL
(2) When a buffer memory is not empty at the time of transmission of the IN direction (reception).
(3) When there is no transmitting data in a buffer memory at the time of transmission of the OUT direction
(transmission).
3.9 Isochronous transfers(PIPE1-2)
The controller is equipped with the following functions pertaining to isochronous transfers.
(1)
Notification of isochronous transfer error information
(2)
Interval counter (specified by the IITV bit)
(3)
Isochronous IN transfer data setup control (IDLY function)
(4)
Isochronous IN transfer buffer flush function (specified by the IFIS bit)
(5)
SOF pulse output function
The controller does not support the High-Bandwidth transfers of isochronous transfers.
相关PDF资料 |
PDF描述 |
|---|---|
| M6XXLFXI | OTHER CLOCK GENERATOR, QCC16 |
| M300LFXIT | 50 MHz, OTHER CLOCK GENERATOR, QCC16 |
| M74HC00C1R | HC/UH SERIES, QUAD 2-INPUT NAND GATE, PQCC20 |
| M74HC157B1N | HC/UH SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDIP16 |
| M74HC158C1 | HC/UH SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PQCC20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M66596WG#RB0Z | 制造商:Renesas Electronics 功能描述:Tray 制造商:Renesas 功能描述:0 |
| M6668 | 制造商:Tamura Corporation of America 功能描述: |
| M66700P | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
| M66700WP | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
| M66701P | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
发布紧急采购，3分钟左右您将得到回复。