参数资料
型号: M66596WG
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封装: 0.80 MM PITCH, FBGA-64
文件页数: 25/133页
文件大小: 1611K
代理商: M66596WG
M66596FP/WG
rev .1.00
2006.3.14
page 118 of 127
4.9.5
DMA access timing (when burst transfer and separate bus are set)
4.9.5.1 DMA burst transfer write timing (CPU bus address not used: DFORM=010)
18
tdis (CTRLH - Dreq)
tw (CTRL_B)
48
tsu (D) th (D)
43
44
DREQi_N
(i=0,1)
DACKi_N
(i=0,1)
D15-D0
Note 5-1
D0
tsu (Dend) th (Dend)
45
46
DENDi_N
(i=0,1)
trec (CTRL_B)
tw (cycle)
49
47
D1
Dn
D2
WR1_N,
WR0_N
17
tdis (CTRL - Dreq)
Note 5-8
4.9.5.2 DMA burst transfer read timing (CPU bus address not used: DFORM=010)
17
tdis (CTRL - Dreq)
tw (CTRL_B)
48
ta (CTRL - D)
tv (CTRL - D)
4
3
DREQi_N
(i=0,1)
DACKi_N
(i=0,1)
RD_N
D15-D0
Note
5-2
D0
ta (CTRL - DendV)
tv (CTRL - DendV)
12
DENDi _N
(i=0,1)
trec (CTRL_B)
tw (cycle)
49
47
D1
11
Dn-1
Dn
Note 5-6
Note 5-8
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