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参数资料
| 型号： | M66596WG |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封装： | 0.80 MM PITCH, FBGA-64 |
| 文件页数： | 118/133页 |
| 文件大小： | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 83 of 127
3.4.3.3 Zero-Length packet addition mode (DxFIFO port writing direction)
With this controller, it is possible to add and send one Zero-Length packet after all of the data has been sent,
under the conditions noted below, by setting “1” for the DEZPM bit of the DxFIFOSEL register. This function can
be set only if the buffer memory writing direction has been set (a pipe in the sending direction has been set for
the CURPIPE bit).
If the number of data bytes written to the buffer memory is a multiple of the integer for the maximum packet
size when the DEND signal is received
3.4.3.4 DEND pin
The controller is able to terminate DMA transfers that used the DEND pin. The DEND pin has separate input
and output functions, depending on the USB data transfer direction.
(1) Buffer memory reading direction
The DEND pin becomes an output pin, making it possible to notify the external DMA controller of the final
data transfer. The conditions under which the DEND signal is asserted can be set using the PKTM bit of
DMAxCFG
register.
Table 3.19 shows the DEND pin assertion conditions for the controller.
Table 3.19 DEND pin assertions
Event
PKTM
Transaction
count ended
BRDY
generated upon
reception of
packet
Reception of short
packet other than
Zero-Length packet
Reception of
Zero-Length
packet when buffer
is not empty
Reception of
Zero-Length packet
when buffer is
empty
*1
0
Asserted
Not asserted
Asserted
1
Asserted
Not asserted
*1) With reception of a Zero-Length packet when the buffer is empty, the DREQ signal is not asserted.
(2) Buffer memory writing direction
The DEND pin becomes the input pin, and data can be sent from the buffer memory (the same situation as
when “BVAL=1” is set).
3.4.3.5 DxFIFO auto clear mode (DxFIFO port reading direction)
If “1” is set for the DCLRM bit of the DxFIFOSEL register, the controller automatically clears the buffer
memory of the pertinent pipe when reading of the data from the buffer memory has been completed.
Table 3.20 shows the packet reception and buffer memory clearing processing for each of the various settings.
Using the DCLRM bit eliminates the need for the buffer to be cleared by software even if a situation occurs
that necessitates clearing of the buffer. This makes it possible to carry out DMA transfers without involving the
control program. This function can be set only in the buffer memory reading direction.
Table 3.20 Packet reception and buffer memory clearing processing
DCLRM = “0”
DCLRM = “1”
Register setting
Buffer status when packet is received
BFRE=0
BFRE=1
BFRE=0
BFRE=1
Buffer full
Doesn’t need to
be cleared
Doesn’t need to
be cleared
Doesn’t need to
be cleared
Doesn’t need to
be cleared
Zero-Length packet reception
Needs to be
cleared
Needs to be
cleared
Doesn’t need to
be cleared
Doesn’t need to
be cleared
Normal short packet reception
Doesn’t need to
be cleared
Needs to be
cleared
Doesn’t need to
be cleared
Doesn’t need to
be cleared
Transaction count ended
Doesn’t need to
be cleared
Needs to be
cleared
Doesn’t need to
be cleared
Doesn’t need to
be cleared
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