- 您现在的位置：买卖IC网 > PDF目录45052 > M66596WG UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 PDF资料下载
参数资料
| 型号： | M66596WG |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封装： | 0.80 MM PITCH, FBGA-64 |
| 文件页数： | 51/133页 |
| 文件大小： | 1611K |
| 代理商： | M66596WG |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页当前第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页
M66596FP/WG
rev .1.00
2006.3.14
page 22 of 127
2.4.1
USB data bus control
Each bit of the DVSTCTR register can be used to control and confirm the state of the USB data bus based on
the user system.
(a) Remote wakeup (Peripheral mode)
The WKUP bit handles control of remote wakeup signal output to the USB bus. The controller controls the
output time for remote wakeup signals. 2ms after a software has set “1” for the WKUP bit, the M66596 outputs a
10 ms “K-State” then it transfers the bus state to idle. When the bus state is transferred to the idle state, the
controller sets “WKUP=0”.
According to the USB specification, USB idle state must be kept longer than 5ms. Thus if the software set
“WKUP=1” right after detection of Suspend state, the controller will assert “K-State” after 2ms.
(b) Remote wakeup, Resume (Host mode)
A resume signal is output on a USB bus by setting a RESUME bit as 1.
Moreover, when the RWUPE bit is set as 1 and a remote wakeup signal is detected, a resume signal is
outputted to a down port. At this time, a controller sets 1 as a "RESUME" bit. In both cases manage the output
time of a resume signal by S/W. The output of a resume signal is stopped by "RWUP=0" or "RESUME=0" writing
by S/W.
(c)
USB Communication enable (Host mode)
A SOF (or uSOF) packet is transmitted on a USB bus by a UACT bit. The controller manages a SOF packet
interval. When "1" is set as a UACT bitthe SOF packet is sent out. When "0" is set as a UACT bit, after sending
out the next SOF, the controller is made into a bus idle state.
(d) USB bus reset (Host mode)
A USB bus reset signal is outputted by setting a USBRST bit as 1. Software should manage USB bus reset
time. Please set "USBRST=0" after waiting for USB bus reset time.
2.4.2
Communication speed discrimination
If the HSE bit of a SYSCFG register is set as 1, at the time of transmission and reception of USB bus reset,
this controller execute a reset handshake automatically and determine transmission speed. Softwear is able to
confirm the USB speed, using the RHST bit.
If Hi-Speed operation has been set to the disabled state (“HSE=0”) by softwere, the controller immediately
establishes Full-Speed operation (“RHST=10”), without executing the reset handshake protocol.
In the Host mode, it is the following timing that a result is reflected in a RHST bit after USB reset is desabled.
Software needs to wait connected peripheral is Full-Speed device.
- Full-Speed device : When a USB bus changes from the SE0 State to J State by with USB bus reset.
- Hi-Speed device : When termination resistance is changed to Hi-Speed mode by the reset handshake.
(It decides during USB bus reset)
After the USB bus reset end (after URST=0 setup), when RHST is not decided after sufficient waiting time,
the USB cable may be disconnect during USB bus reset. In such a case, please check the state of a USB bus by
the LNST bit.
2.4.3
Test mode
Table 2.6 shows the test mode operation of the controller. The UTST bit of the TESTMODE register controls
the USB test signal output during Hi-Speed operation.
Table 2.6 Test mode operation
UTST bit setting
Test mode
Peripheral mode
Host mode
Normal operation
0000
Test_J
0001
1001
Test_K
0010
1010
Test_SE0_NAK
0011
1011
Test_Packet
0100
1100
Reserved
0101-0111
1101-0111
相关PDF资料 |
PDF描述 |
|---|---|
| M6XXLFXI | OTHER CLOCK GENERATOR, QCC16 |
| M300LFXIT | 50 MHz, OTHER CLOCK GENERATOR, QCC16 |
| M74HC00C1R | HC/UH SERIES, QUAD 2-INPUT NAND GATE, PQCC20 |
| M74HC157B1N | HC/UH SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDIP16 |
| M74HC158C1 | HC/UH SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PQCC20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M66596WG#RB0Z | 制造商:Renesas Electronics 功能描述:Tray 制造商:Renesas 功能描述:0 |
| M6668 | 制造商:Tamura Corporation of America 功能描述: |
| M66700P | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
| M66700WP | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
| M66701P | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
发布紧急采购，3分钟左右您将得到回复。