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参数资料
| 型号： | CORE10/100-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 13/106页 |
| 文件大小： | 0K |
| 描述： | IP CORE10/100 ETHERNET MAC |
| 标准包装： | 1 |
| 系列： | * |
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Core10100 v4.0
CSR – Control/Status Register Logic
The CSR component is used to control Core10100 operation by the host. It implements the CSR register set and the
interrupt controller. It also provides a generic host interface supporting 8-, 16-, and 32-bit transfer. The CSR
component operates synchronously with the clkcsr clock from the host CSR interface. The CSR also provides a Serial
ROM interface and MII Management interface. The host can access these two interfaces via read/write CSR registers.
DMA – Direct Memory Access Controller
The direct memory access controller implements the host data interface. It services both the receive and transmit
channels. The TLSM and TFIFO have access to one DMA channel. The RLSM and RFIFO have access to the other
DMA channel. The direct memory access controller operates synchronously with the CLKDMA clock from the host
data interface.
TLSM – Transmit Linked List State Machine
The transmit linked list state machine implements the descriptor/buffer architecture of Core10100. It manages the
transmit descriptor list and fetches the data prepared for transmission from the data buffers into the transmit FIFO. The
transmit linked list state machine controller operates synchronously with the CLKDMA clock from the host data
interface.
TFIFO – Transmit FIFO
The transmit FIFO is used for buffering data prepared for transmission by Core10100. It provides an interface for the
external transmit data RAM working as FIFO memory. It fetches the transmit data from the host via the DMA
interface. The FIFO size can be configured via the core parameters. The transmit FIFO controller operates
synchronously with the CLKDMA clock from the host data interface.
TC – Transmit Controller
The transmit controller implements the 802.3 transmit operation. From the network side, it uses the standard 802.3 MII
interface for an external PHY device. The TC unit reads transmit data from the external transmit data RAM, formats
the frame, and transmits the framed data via the MII. The transmit controller operates synchronously with the CLKT
clock from the MII interface.
BD – Backoff/Deferring
The backoff/deferring controller implements the 802.3 half-duplex operation. It monitors the status of the Ethernet bus
and decides whether to perform a transmit or backoff/deferring of the data via the MII. It operates synchronously with
the CLKT clock from the MII interface.
RLSM – Receive Linked List State Machine
The receive linked list state machine implements the descriptor/buffer architecture of Core10100. It manages the receive
descriptor list and moves the data from the receive FIFO into the data buffers. The receive linked list state machine
controller operates synchronously with the clkdma clock from the host data interface.
RFIFO – Receive FIFO
The receive FIFO is used for buffering data received by Core10100. It provides an interface for the external RAM
working as FIFO memory. The FIFO size can be configured by the generic parameters of the core. The receive FIFO
controller operates synchronously with the CLKDMA clock from the host data interface.
v4.0
13
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CORE10GMAC-OM | 功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1 |
| CORE10GMAC-OMFL | 功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1 |
| CORE12X4 | 制造商:Bogen Communications 功能描述:12 X 4 MATRIX CONTROLLER |
| CORE1553BBC-AN | 功能描述:IP MODULE CORE1553 BUS CTLR RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| CORE1553BBC-AR | 功能描述:IP MODULE CORE1553 BUS CTLR RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
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