- 您现在的位置：买卖IC网 > PDF目录16069 > CORE10/100-RM (Microsemi SoC)IP CORE10/100 ETHERNET MAC PDF资料下载
参数资料
| 型号： | CORE10/100-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 55/106页 |
| 文件大小： | 0K |
| 描述： | IP CORE10/100 ETHERNET MAC |
| 标准包装： | 1 |
| 系列： | * |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页当前第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页
Core10100 v4.0
Start Receive
Command
Receive
Stopped
Internal Operation
Reset
Command
Stop Receive
Command
Stop Receive
Command
Receive
Running
Frame
Recognized
Pull Demand
Command
Reset
Command
Receive
Suspended
Descriptor
Unavailable
Figure 4-7 · Receive Process Transitions
Note: Refer to the Core10100 User’s Guide for an example of receive timing.
A typical data flow in a receive process is illustrated in Figure 4-8 on page 55 . The events for the receive process typically
happen in the following order:
1.
2.
3.
4.
5.
6.
7.
The host sets up CSR registers for the operational mode, interrupts, etc.
The host sets up receive descriptors in the shared RAM.
The host sends the receive start command.
Core10100 starts to fetch the transmit descriptors.
Core10100 waits for receive data on MII.
Core10100 transfers received data to the Receive Data RAM.
Core10100 transfers received data to shared RAM from Receive Data RAM.
Host-SharedRAM
Rx Des
CSR_Interface
CSRs
CSR6
Data_Interface-SharedRAM
Data_Interface-RxFIFO_RAM
RxFIFO_RAM-Receive_Controller
Rx Des
Rx Data
Rx Data
Rx Data
CRC
Receive_Controller-MII
Preamble
Rx Data
CRC
Figure 4-8 · Receive Data Flow
Interrupt Controller
The interrupt controller uses three internal Control and Status registers: CSR5, CSR7, and CSR11. CSR5 contains the
Core10100 status information. It has 10 bits that can trigger an interrupt. These bits are collected in two groups: normal
interrupts and abnormal interrupts. Each group has its own summary bit, NIS and AIS, respectively. The NIS and AIS
bits directly control the int output port of Core10100. Every status bit in CSR5 that can source an interrupt can be
individually masked by writing an appropriate value to CSR7 (Interrupt Enable register).
Additionally, an interrupt mitigation mechanism is provided for reducing CPU usage in servicing interrupts. Interrupt
mitigation is controlled via CSR11. There are separate interrupt mitigation control blocks for the transmit and receive
interrupts. Both of these blocks consist of a 4-bit frame counter and a 4-bit timer. The operation of these blocks is
similar for the receive and transmit processes. After the end of a successful receive or transmission operation, an
v4.0
55
相关PDF资料 |
PDF描述 |
|---|---|
| M3CMK-2040K | IDC CABLE - MKC20K/MC20F/MCG20K |
| M3AMK-2040K | IDC CABLE - MSC20K/MC20F/MCG20K |
| M3UUK-4020K | IDC CABLE - MKS40K/MC40F/MKS40K |
| BQ26221PWG4 | IC BATTERY MONITOR HP 8-TSSOP |
| MAX6328UR29+T | IC MPU/RESET CIRC 2.93V SOT23-3 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CORE10GMAC-OM | 功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1 |
| CORE10GMAC-OMFL | 功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1 |
| CORE12X4 | 制造商:Bogen Communications 功能描述:12 X 4 MATRIX CONTROLLER |
| CORE1553BBC-AN | 功能描述:IP MODULE CORE1553 BUS CTLR RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| CORE1553BBC-AR | 功能描述:IP MODULE CORE1553 BUS CTLR RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
发布紧急采购，3分钟左右您将得到回复。