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参数资料
型号： CORE10/100-RM
厂商： Microsemi SoC
文件页数： 97/106页
文件大小： 0K
描述： IP CORE10/100 ETHERNET MAC
标准包装： 1
系列： *
C
List of Document Changes
The following table lists critical changes that were made in the current version of the document.
Previous
Version
v3.1
Changes in Current Version (v4.0)
The core name Core10/100 was changed to Core10100, and Core10/100-AHB was changed to Core10100_AHB.
The core version was changed from v3.2 to v4.0.
Figure 1 · Core10100 Block Diagram and Figure 2 · Typical Core10100 Application were updated to change MII to
RMII/MII.
Figure 3 · ARM-Based System Using Core10100_AHBAPB was replaced.
Instances of CoreConsole were changed to SmartDesign throughout the document.
Table 1 · Core10100 Device Utilization and Performance for an 8-Bit Datapath through Table 6
· Core10100_AHBAPB Device Utilization and Performance for a 32-Bit Datapath were updated.
Table 7 · Parameter Settings was revised to update the TFIFODEPTH and RFIFODEPTH values. A row was
added for RMII. The DATADEPTH parameter value was changed to 20 for the 8-bit cores.
Figure 1-1 · Core 10100 Architecture and Figure 1-2 · Core10100_AHBAPB Architecture were revised to add an
MII to RMII block.
The “CSR – Control/Status Register Logic” section was revised to remove reference to the power management
functionality of Core10100.
The “Licensing” section was revised to remove the Evaluation version. The CoreConsole section was removed.
Figure 2-1 · Core10100 Configuration within SmartDesign and Figure 2-2 · Core10100_AHBAPB Configuration
within SmartDesign replaced previous figures of configuration in CoreConsole. The “Importing into Libero IDE”
section and “Simulation Flows” section were updated. The “Synthesis in Libero IDE” section is new.
The introduction to the “Interface Descriptions” section was revised to list interfaces as CSR and AMBA instead of
legacy, AHB, and APB.
ProASIC3L was added to the values for the FAMILY parameter in Table 3-1 · Core10100 Parameters . A default
value column was added. The acceptable values were revised for the following parameters: DATADEPTH,
TCDEPTH, RCDEPTH, TFIFODEPTH, and RFIFODEPTH. The description was revised for TCDEPTH
and RCDEPTH.
A default value column was added to Table 3-2 · Core10100_AHBAPB Parameters . Acceptable values were revised
for the following parameters: AHB_AWIDTH, TCDEPTH, RCDEPTH, TFIFODEPTH, and
RFIFODEPTH. The description was revised for TCDEPTH and RCDEPTH.
The section title “Legacy Interface Signals” was changed to “CSR Interface Signals” . Table 3-3 · Core10100 Signals
and Table 3-4 · Signals Included in Core10100 and Core10100_AHBAPB were revised to change signal names to
all capital letters. The subheading “MII PHY Interface” in Table 3-4 was revised and is now “RMII/MII PHY
Interface.” Three signal names changed: rxer to RX_ER, rxdv to RX_DV, and txen to TX_EN. The descriptions
were revised to include RMII for RMII_CLK and CRS_DV. The descriptions for CLKT, CLKR, RX_ER,
RXD,TXD, and RMII_CLK were revised in Table 3-4 · Signals Included in Core10100 and
Core10100_AHBAPB .
Table 3-5 · Core10100_AHBAPB Signals was moved to the end of the chapter.
The reset value for CSR9 was changed to FFF483FFH in Table 4-1 · CSR Locations .
The permissible values were changed for PBL in Table 4-3 · Bus Mode Register Bit Functions . 1 and 2 are no
longer permissible values.
v4.0
Page
N/A
5
6
N/A
7 – 8
10
11 – 12
13
15 – 18
19
19
20
22 – 24
27
28
97
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