参数资料
型号: CORE10/100-RM
厂商: Microsemi SoC
文件页数: 36/106页
文件大小: 0K
描述: IP CORE10/100 ETHERNET MAC
标准包装: 1
系列: *
Software Interface
Table 4-18 lists the transmit FIFO threshold levels. These levels are specified in bytes.
Table 4-18 · Transmit FIFO Threshold Levels (bytes)
Core10100 v4.0
CSR6.21
0
0
0
0
1
CSR6.15..14
00
01
10
11
xx
CSR6.22 = 1
64
128
128
256
Store and forward
CSR6.22 = 0
128
256
512
1024
Store and forward
Table 4-19 · Interrupt Enable Register (CSR7)
Bits 31:24
Bits 23:16
NIE
Bits 15:8
AIE
ERE
GTE
ETE
RSE
Bits 7:0
RUE
RIE
UNE
TUE
TSE
TIE
Note:
The CSR7 register has unimplemented bits (shaded). If these bits are read, they will return a predefined value. Writing to
these bits has no effect.
Table 4-20 · Interrupt Enable Register Bit Function
36
Bit
CSR7.16
CSR7.15
CSR7.14
Symbol
NIE
AIE
ERE
Function
Normal interrupt summary enable
When set, normal interrupts are enabled. Normal interrupts are listed below:
CSR5.0 – Transmit interrupt
CSR5.2 – Transmit buffer unavailable
CSR5.6 – Receive interrupt
CSR5.11 – General-purpose timer expired
CSR5.14 – Early receive interrupt
Abnormal interrupt summary enable
When set, abnormal interrupts are enabled. Abnormal interrupts are listed below:
CSR5.1 – Transmit process stopped
CSR5.5 – Transmit underflow
CSR5.7 – Receive buffer unavailable
CSR5.8 – Receive process stopped
CSR5.10 – Early transmit interrupt
Early receive interrupt enable
When both the ERE and NIE bits are set, early receive interrupt is enabled.
v4.0
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