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| 型号： | CORE10/100-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 35/106页 |
| 文件大小： | 0K |
| 描述： | IP CORE10/100 ETHERNET MAC |
| 标准包装： | 1 |
| 系列： | * |
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Core10100 v4.0
Table 4-16 · Operation Mode Register Bit Functions (continued)
Register Maps
Bit
CSR6.1
CSR6.0
Symbol
SR
HP
Function
Start/stop receive command
Setting this bit enables the reception of the frame by Core10100 and the frame is
written into the receive FIFO. If the bit is not enabled, then the frame is not written
into the receive FIFO.
Setting this bit when the receive process is in a stopped state causes a transition into a
running state. In the running state, Core10100 checks the receive descriptor at the
current descriptor list position. If Core10100 owns the descriptor, it can process an
incoming frame. When the host owns the descriptor, the receiver enters a suspended
state and also sets the CSR5.7 (receive buffer unavailable) bit.
Clearing this bit when the receive process is in a running or suspended state instructs
Core10100 to enter a stopped state after receiving the current frame.
Core10100 does not go into the stopped state immediately after clearing the SR bit.
Core10100 will finish all pending receive operations before going into the stopped
state. The status bits of the CSR5 register should be read to check the actual receive
operation state.
Hash/perfect receive filtering mode (read-only)
0 – Perfect filtering of the incoming frames is performed according to the physical
addresses specified in a setup frame.
1 – Imperfect filtering over the frames with the multicast addresses is performed
according to the hash table specified in a setup frame.
A physical address check is performed according to the CSR6.2 (HO, hash-only) bit.
When both the HO and HP bits are set, an imperfect filtering is performed on all of
the addresses.
The “filtering type” bits of the setup frame determine the state of this bit.
Table 4-17 lists all possible combinations of the address filtering bits. The actual values of the IF, HO, and HP bits are
determined by the filtering type (FT1–FT0) bits in the setup frame, as shown in Table 4-37 on page 50 . The IF, HO,
and HP bits are read-only.
Table 4-17 · Receive Address Filtering Modes Summary
PM PR IF HO HP
CSR6.7 CSR6.6 CSR6.4 CSR6.2 CSR6.0
Current Filtering Mode
0
0
0
0
x
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
0
x
1
x
1
16 physical addresses – perfect filtering mode
One physical address for physical addresses and 512-bit hash
table for multicast addresses
512-bit hash table for both physical and multicast addresses
Inverse filtering
Promiscuous mode
Promiscuous mode
Pass all multicast frames
Pass all multicast frames
v4.0
35
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