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| 型号： | CORE10/100-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 32/106页 |
| 文件大小： | 0K |
| 描述： | IP CORE10/100 ETHERNET MAC |
| 标准包装： | 1 |
| 系列： | * |
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Software Interface
Table 4-14 · Status Register Bit Functions (continued)
Core10100 v4.0
32
Bit
CSR5.14
CSR5.11
CSR5.10
CSR5.8
CSR5.7
CSR5.6
CSR5.5
CSR5.2
Symbol
ERI
GTE
ETI
RPS
RU
RI
UNF
TU
Function
Early receive interrupt
Set when Core10100 fills the data buffers of the first descriptor.
The user can clear this bit by writing a 1. Writing a 0 has no effect.
General-purpose timer expiration
Gets set when the general-purpose timer reaches zero value.
The user can clear this bit by writing a 1. Writing a 0 has no effect.
Early transmit interrupt
Indicates that the packet to be transmitted was fully transferred into the FIFO.
The user can clear this bit by writing a 1. Writing a 0 has no effect.
Receive process stopped
RPS is set when a receive process enters a stopped state.
The user can clear this bit by writing a 1. Writing a 0 has no effect.
Receive buffer unavailable
When set, indicates that the next receive descriptor is owned by the host and is
unavailable for Core10100. When RU is set, Core10100 enters a suspended state and
returns to receive descriptor processing when the host changes ownership of the
descriptor. Either a receive-poll-demand command is issued or a new frame is recognized
by Core10100.
The user can clear this bit by writing a 1. Writing a 0 has no effect.
Receive interrupt
Indicates the end of a frame receive. The complete frame has been transferred into the
receive buffers. Assertion of the RI bit can be delayed using the receive interrupt
mitigation counter/timer (CSR11.NRP/CSR11.RT).
The user can clear this bit by writing a 1. Writing a 0 has no effect.
Transmit underflow
Indicates that the transmit FIFO was empty during a transmission. The transmit process
goes into a suspended state.
The user can clear this bit by writing a 1. Writing a 0 has no effect.
Transmit buffer unavailable
When set, TU indicates that the host owns the next descriptor on the transmit descriptor
list; therefore, it cannot be used by Core10100. When TU is set, the transmit process goes
into a suspended state and can resume normal descriptor processing when the host
changes ownership of the descriptor. Either a transmit-poll-demand command is issued
or transmit automatic polling is enabled.
The user can clear this bit by writing a 1. Writing a 0 has no effect.
v4.0
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