参数资料
型号: CORE10/100-RM
厂商: Microsemi SoC
文件页数: 58/106页
文件大小: 0K
描述: IP CORE10/100 ETHERNET MAC
标准包装: 1
系列: *
Software Interface
Table 4-40 · External PHY Interface Signals (continued)
Core10100 v4.0
IEEE 802.3 Core10100
Signal Name Signal Name
Description
Collision detected
This signal must be asserted by the PHY when a collision is detected on the
COL
CRS
TX_ER
MDC
MDIO
COL
CRS
TX_ER
MDC
MDI
MDO
medium. It is valid only when operating in a half-duplex mode. When operating in a
full-duplex mode, this signal is ignored by Core10100.
The COL signal is not required to be synchronous to either CLKR or CLKT.
The COL signal is sampled internally by the CLKT clock.
Carrier sense
This signal must be asserted by the PHY when either a receive or a transmit medium
is non-idle.
The CRS signal is not required to be synchronous to either CLKR or CLKT.
Transmit error
The current version of Core10100 has the TX_ER signal statically tied to logic 0 (no
transmit errors).
MII management clock
This signal is driven by the CSR9.16 bit.
MII management data input
The state of this signal can be checked by reading the CSR9.19 bit.
MII management data output
This signal is driven by the CSR9.18 bit.
MII Receive Operation
CLKR
RX_DV
RX_ER
Read Points
Error Detected
RXD[3:0]
data
data
data
data
Figure 4-10 · MII Receive Operation
58
v4.0
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