参数资料
型号: CORE10/100-RM
厂商: Microsemi SoC
文件页数: 65/106页
文件大小: 0K
描述: IP CORE10/100 ETHERNET MAC
标准包装: 1
系列: *
5
Interface Timing
Core10100—CSR Interface
CSR Read/Write Operation
The CSR read and write operations are synchronous to the positive edge of the CLKCSR signal and are illustrated in
Figure 5-1 . Read operations require that the data be read in the same clock cycle in which the csrreq signal is set to
logic 1.
CLK
CSRREQ
CSRRW
Read
Write
Read
CSRBE
CSRADDR
CSRDATAI
CSRDATAO
BE
ADDR
DATA
BE
ADDR
DATA
BE
ADDR
DATA
Figure 5-1 · CSR Read/Write Operation
Core10100—Data Interface
The data interface is used for data transfers between Core10100 and external shared system memory. It is a master via
the DMA interface; i.e., Core10100 operates as an initiator on this data interface. The interface operates synchronously
with the CLKDMA clock supplied by the system. The data width of the interface can be changed using the core
parameter DATAWIDTH. Possible DATAWIDTH values are 8, 16, and 32. There are two data exchange types that
can be initiated and performed by Core10100 via the DMA interface. The first data exchange type is the transmit and
receive descriptors. These are set up by the host and fetched by the DMA interface to instruct Core10100 to exchange
the Ethernet frame data in specified locations of shared RAM. The second data exchange type is the Ethernet data type.
Data Interface Write Operation
The data interface supports single or burst data transfer. The writes are operated on the positive edge of the clock
CLKDMA. The write operation starts when the data interface sets DATAREQ to HIGH, and then the data interface
waits until DATAACK from the host interface is set to HIGH (which indicates that the host is ready to receive the
writes). A byte enable signal DATABE indicates the valid bytes on each write. The signal DATAOB indicates to the
hosts that it is the end of a burst transfer. The signal DATAACK can be asserted or deasserted at any clock cycle; even in
the middle of a burst transfer.
v4.0
65
相关PDF资料
PDF描述
M3CMK-2040K IDC CABLE - MKC20K/MC20F/MCG20K
M3AMK-2040K IDC CABLE - MSC20K/MC20F/MCG20K
M3UUK-4020K IDC CABLE - MKS40K/MC40F/MKS40K
BQ26221PWG4 IC BATTERY MONITOR HP 8-TSSOP
MAX6328UR29+T IC MPU/RESET CIRC 2.93V SOT23-3
相关代理商/技术参数
参数描述
CORE10GMAC-OM 功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1
CORE10GMAC-OMFL 功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1
CORE12X4 制造商:Bogen Communications 功能描述:12 X 4 MATRIX CONTROLLER
CORE1553BBC-AN 功能描述:IP MODULE CORE1553 BUS CTLR RoHS:否 类别:编程器,开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384
CORE1553BBC-AR 功能描述:IP MODULE CORE1553 BUS CTLR RoHS:否 类别:编程器,开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384