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参数资料
型号： CORE10/100-RM
厂商： Microsemi SoC
文件页数： 98/106页
文件大小： 0K
描述： IP CORE10/100 ETHERNET MAC
标准包装： 1
系列： *
List of Document Changes
Core10100 v4.0
Previous
Version
v3.1
(cont ’d)
v3.0
v2.3
v2.2
98
Changes in Current Version (v4.0)
The function for TTM was revised to add information about RMII mode in Table 4-16 · Operation Mode Register
Bit Functions .
In Table 4-23 · MII Management and Serial ROM Interface Register (CSR9), MII was changed to MDEN.
The title of Figure 4-1 · I/O Tristate Buffer Connections was changed from “External Tristate Buffer Connections.”
The function for CON was revised to add information about when the bit should be written in Table 4-26
· General-Purpose Timer and Interrupt Mitigation Control Bit Functions .
The description for RX_ER was revised in Table 4-40 · External PHY Interface Signals .
The “MII to RMII Interface” section was revised to state the internal clock net CLK_TX_RX must be assigned to
a global clock network. The CLK_TX_RX was added to Figure 4-16 · MII_TO_RMII Internal Architecture .
Figure 5-6 · Simple Transfer is new.
The “Core10100-RMII Interface” section is new.
The Verification Testbench section was removed. References to the Evaluation release of Core10100 were removed
from the “Testbench Operation and Modification” section .
The “Usage with Cortex?-M1” section replaced the “Usage with CoreMP7” section.
The “Software Drivers” chapter of the handbook was deleted. It contained only the following text: “Example
software drivers are available from Actel for Core10100. Contact Actel Technical Support for information
( tech@actel.com ).”
The “Verification Tests Description” Appendix was removed.
All references to the Core100100 datasheet were removed, as it has been superseded by the Core10100 Handbook.
The “Memory Blocks” section was updated to add information on the MII and RMII.
The RMII parameter was added to Table 3-1 · Core10100 Parameters and Table 3-2 · Core10100_AHBAPB
Parameters .
The RMII_CLK and CRS_DV signals were added to Table 3-4 · Signals Included in Core10100 and
Core10100_AHBAPB .
The descriptions for CSR6.13 and CSR6.1 were updated in Table 4-16 · Operation Mode Register Bit Functions .
The description for CSR8.(15..0) was updated in Table 4-22 · Missed Frames and Overflow Counter Bit Functions .
A new sentence was added to the end of the “MAC Address and Setup Frames” section regarding setup frame
buffer size.
The first three rows of Table 4-38 · Perfect Filtering Setup Frame Buffer were revised.
The sentence, “Before writing to CSR4, the MAC must be in a stopped state” was added to the “Transmit Process”
section . The sentence, “Before writing to CSR3, the MAC must be in a stopped state” was added to the “Receive
Process” section . A sentence was also added to clarify when the receive state machine goes into a stopped state.
The following sentence was added to the “Receive Address Filtering” section : “To receive the broadcast frame, the
hash table bit corresponding to the broadcast address CRC value should be set.”
The “Steps for Calculating CRC with Hash Filtering” section is new.
The “MII to RMII Interface” section is new.
The “Supported Device Families” section was added and the “Memory Requirements” section was updated to
include ProASIC3L.
v4.0
Page
33
38
39
40
57
64
68
68
71
73
N/A
N/A
N/A
14
19 , 20
24
33
38
49
50
52 , 54
62
63
64
7 , 10
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