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| 型号： | CORE10/100-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 63/106页 |
| 文件大小： | 0K |
| 描述： | IP CORE10/100 ETHERNET MAC |
| 标准包装： | 1 |
| 系列： | * |
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Core10100 v4.0
Internal Operation
Steps for Calculating CRC with Hash Filtering
Following are the steps the core is using, and Testbench/Software needs to follow. These are the steps for calculating
CRC with which the hash filter logic of the DUT accepts the frames properly:
1.
2.
3.
4.
5.
6.
Initial value of the CRC is 0xFFFFFFFF.
XOR the incoming data bit with the 31st bit of the current CRC value.
Left shift the current CRC value by one bit.
Check the XORed value from step 2. If this value is 1'b1 then XOR the current CRC value with the generator
polynomial (0x4C11DB7).
Insert the bit value result from step 2 at the 0th bit location of the current CRC value.
Repeat steps 2, 3, 4, and 5 until the CRC is calculated for all the bits of the data.MII_TO_RMII Internal
Architecture
External Address Filtering Interface
An external address filtering interface is provided to extend the internal filtering capabilities of Core10100. The interface
allows connection of external user-supplied address checking logic. All signals from the interface are synchronous to the
clkr clock.
If the external address filtering is not used, all input ports of the interface must be grounded and all output ports must be
left floating.
Table 4-42 · External Address Interface Description
Core10100
Signal Name
MATCH
MATCHVAL
MATCHEN
MATCHDATA
Type
In
In
Out
Out
Description
External address match
When HIGH, indicates that the destination address on the MATCHDATA port is
recognized by the external address checking logic and that the current frame should
be received by Core10100.
When LOW, indicates that the destination address on the MATCHDATA port is
not recognized and that the current frame should be discarded.
Note that the MATCH signal should be valid only when the MATCHVAL signal
is HIGH.
External address match valid
When HIGH, indicates that the MATCH signal is valid.
External match enable
When HIGH, indicates that the MATCHDATA signal is valid. The MATCHEN
output should be used as an enable signal for the external address checking logic. It
is HIGH for at least four CLKR clock periods to allow for latency of external
address checking logic.
External address match data
The MATCHDATA signal represents the 48-bit destination address of the received
frame.
Note that the MATCHDATA signal is valid only when matchen signal is HIGH.
v4.0
63
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| CORE10GMAC-OM | 功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1 |
| CORE10GMAC-OMFL | 功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1 |
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| CORE1553BBC-AR | 功能描述:IP MODULE CORE1553 BUS CTLR RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
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