参数资料
型号: CORE10/100-RM
厂商: Microsemi SoC
文件页数: 92/106页
文件大小: 0K
描述: IP CORE10/100 ETHERNET MAC
标准包装: 1
系列: *
Transmit and Receive Functional Timing Examples
Core10100 v4.0
Transmit on MII with 32-Bit Transmit Data RAM
(1), (2) Core10100 sends out requested read addresses. t0 is eight cycles.
(3), (4) t1 is the time between Core10100 sending out a read address request and the appearance of the requested data on
MII.
(1)
t 0
(2)
(3)
t 1
(4)
CLKT
TX_EN
TRADDR[8:0]
TRDATA[31:0]
001
00000004
002
00000008
003
0000000C
004
00000010
TXD[3:0]
5
0
4 0
8 0
C
Figure B-9 · Transmit on MII with 32-Bit Transmit Data RAM
Transmit on MII with 16-Bit Transmit Data RAM
(1), (2) Core10100 sends out requested read addresses. t0 is four cycles.
(3), (4) t1 is the time between Core10100 sending out a read address request and the appearance of the requested data on
MII.
(1)
t 0
(2)
(3)
t 1
(4)
CLKT
TX_EN
TRADDR[9:0] 000
TRDATA[15:0] 0000
TXD[3:0] 5
001
D
002
0004
0
003
0000
4
004
0008
0
Figure B-10 · Transmit on MII with 16-Bit Transmit Data RAM
Transmit on MII with 8-Bit Transmit Data RAM
(1), (2) Core10100 sends out requested read addresses. t0 is two cycles.
(3), (4) t1 is the time between Core10100 sending out a read address request and the appearance of the requested data on
MII.
(1)
t 0
(2)
(3)
t 1
(4)
CLKT
TRADDR[10:0]
001
002
003
004
005
006
TRDATA[7:0] 00
TX_EN
04
TXD[3:0] 5
D
0
4
Figure B-11 · Transmit on MII with 8-Bit Transmit Data RAM
92
v4.0
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