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| 型号： | CORE10/100-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 25/106页 |
| 文件大小： | 0K |
| 描述： | IP CORE10/100 ETHERNET MAC |
| 标准包装： | 1 |
| 系列： | * |
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Core10100 v4.0
Parameters on Core10100_AHBAPB
Table 3-4 · Signals Included in Core10100 and Core10100_AHBAPB (continued)
Name
Type
Polarity /
Bus Size
Description
Clock for receive operation
CLKR
In
Rise
This must be a 25 MHz clock for a 100 Mbps operation or a 2.5 MHz clock for a 10 Mbps
operation. This input is only used in MII mode. In RMII mode, this input will be grounded by
SmartDesign.
Receive error
RX_ER
In
HIGH
If RX_ER is asserted during Core10100 reception, the frame is received and status of the frame
is updated with RX_ER.
The RX_ER signal must be synchronous to the CLKR receive clock.
Receive data valid signal
RX_DV
In
HIGH
The PHY device must assert RX_DV when a valid data nibble is provided on the RXD signal.
The RX_DV signal must be synchronous to the CLKR receive clock.
Collision detected
This signal must be asserted by the PHY when a collision is detected on the medium. It is valid
COL
In
HIGH
only when operating in a half-duplex mode. When operating in a full-duplex mode, this signal
is ignored by Core10100.
The COL signal is not required to be synchronous to either CLKR or CLKT.
The COL signal is sampled internally by the CLKT clock.
Carrier sense
CRS
In
HIGH
This signal must be asserted by the PHY when either a receive or transmit medium is non-idle.
The CRS signal is not required to be synchronous with either CLKR or CLKT.
MDI
In
1
MII management data input
The state of this signal can be checked by reading the CSR9.19 bit.
Receive data recovered and decoded by PHY
The RXD[0] signal is the least significant bit.
RXD
In
4
The RXD bus must be synchronous to the CLKR in MII mode. In RMII mode, RXD[1:0] is
used and RXD[3:2] will be grounded by SmartDesign. In RMII mode, RXD[1:0] is
synchronous to RMII_CLK.
Transmit enable
TX_EN
Out
HIGH
When asserted, indicates valid data for the PHY on the TXD port.
The TX_EN signal is synchronous to the CLKT transmit clock.
Transmit error
TXER
Out
HIGH
The current version of Core10100 has the TXER signal statically tied to logic 0 (no transmit
errors).
MDC
MDO
MDEN
Out
Out
Out
Rise
1
HIGH
MII management clock
This signal is driven by the CSR9.16 bit.
MII management data output
This signal is driven by the CSR9.18 bit.
MII management buffer control
v4.0
25
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