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| 型号： | CORE10/100-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 24/106页 |
| 文件大小： | 0K |
| 描述： | IP CORE10/100 ETHERNET MAC |
| 标准包装： | 1 |
| 系列： | * |
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Interface Descriptions
Common Interface Signals
The following signals are included on both the Core10100 and Core10100_AHBAPB cores.
Table 3-4 · Signals Included in Core10100 and Core10100_AHBAPB
Core10100 v4.0
Name
Type
Polarity /
Bus Size
Description
General Host Interface Signal
RSTCSR
INT
RSTTCO
RSTRCO
TPS
RPS
In
Out
Out
Out
Out
Out
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
Host-side reset
Interrupt
Transmit side reset
Receive side reset
Transmit process stopped
Receive process stopped
Serial ROM Interface
SDI
SCS
SCLK
SDO
In
Out
Out
Out
1
1
1
1
Serial data
Serial chip select
Serial clock output
Serial data output
External Address Filtering Interface
External address match
When HIGH, indicates that the destination address on the MATCHDATA port is
recognized by the external address-checking logic and that the current frame must be received
MATCH
In
HIGH
by Core10100.
When LOW, indicates that the destination address on the MATCHDATA port is not
recognized and that the current frame should be discarded.
Note that the match signal should be valid only when the MATCHVAL signal is HIGH.
MATCHVAL
In
HIGH
External address match valid
When HIGH, indicates that the MATCH signal is valid.
External match enable
MATCHEN
Out
HIGH
When HIGH, indicates that the MATCHDATA signal is valid. The MATCHEN output
should be used as an enable signal for the external address-checking logic. It is HIGH for at
least four CLKR clock periods to allow for the latency of external address-checking logic.
External address match data
MATCHDATA
Out
48
The MATCHDATA signal represents the 48-bit destination address of the received frame.
Note that the MATCHDATA signal is valid only when the MATCHEN signal is HIGH.
RMII/MII PHY Interface
Clock for transmit operation
CLKT
In
Rise
This must be a 25 MHz clock for a 100 Mbps operation or a 2.5 MHz clock for a 10 Mbps
operation. This input is only used in MII mode. In RMII mode, this input will be grounded by
SmartDesign.
24
v4.0
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