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| 型号： | CORE10/100-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 57/106页 |
| 文件大小： | 0K |
| 描述： | IP CORE10/100 ETHERNET MAC |
| 标准包装： | 1 |
| 系列： | * |
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Core10100 v4.0
Internal Operation
General-Purpose Timer
Core10100 includes a 16-bit general-purpose timer to simplify time interval calculation by an external host. The timer
operates synchronously with the transmit clock clkt generated by the PHY device. This gives the host the possibility of
measuring time intervals based on actual Ethernet bit time.
The timer can operate in one-shot mode or continuous mode. In one-shot mode, the timer stops after reaching a zero
value; in continuous mode, it is automatically reloaded and continues counting down after reaching a zero value.
The actual count value can be tested with an accuracy of ±1 bit by reading CSR11.(15..0). When writing CSR11.(15..0),
the data is stored in the internal reload register. The timer is immediately reloaded and starts to count down.
Data Link Layer Operation
MII Interface
Core10100 uses a standard MII interface as defined in the 802.3 standard.
This interface can be used for connecting Core10100 to an external Ethernet 10/100 PHY device.
MII Interface Signals
Table 4-40 · External PHY Interface Signals
IEEE 802.3 Core10100
Signal Name Signal Name
Clock for receive operation
Description
RX_CLK
RX_DV
RX_ER
RXD
TX_CLK
TX_EN
TXD
CLKR
RX_DV
RX_ER
RXD
CLKT
TX_EN
TXD
This must be a 25 MHz clock for 100 Mbps operation or a 2.5 MHz clock for 10
Mbps operation.
Receive data valid signal
The PHY device must assert RX_DV when a valid data nibble is provided on the
RXD signal.
The RX_DV signal must be synchronous to the CLKR receive clock.
Receive error
If RX_ER is asserted during Core10100 reception, the frame is received and status
of the frame is updated with RX_ER.
The RX_ER signal must be synchronous to the CLKR receive clock.
Receive data recovered and decoded by PHY
The RXD[0] signal is the least significant bit.
The RXD bus must be synchronous to the CLKR receive clock.
Clock for transmit operation
This must be a 25 MHz clock for 100 Mbps operation or a 2.5 MHz clock for 10
Mbps operation.
Transmit enable
When asserted, indicates valid data for the PHY on TXD.
The TX_EN signal is synchronous to the CLKT transmit clock.
Transmit data
The TXD[0] signal is the least significant bit.
The TXD bus is synchronous to the CLKT transmit clock.
v4.0
57
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