参数资料
型号: CORE10/100-RM
厂商: Microsemi SoC
文件页数: 56/106页
文件大小: 0K
描述: IP CORE10/100 ETHERNET MAC
标准包装: 1
系列: *
Software Interface
Core10100 v4.0
appropriate counter is decremented and the timer starts to count down if it has not already started. An interrupt is
triggered when either the counter or the timer reaches a zero value. This allows Core10100 to generate a single interrupt
for a few received/transmitted frames or after a specified time since the last successful receive/transmit operation.
It is possible to omit transmit interrupt mitigation for one particular frame by setting the Interrupt on Completion (IC)
bit in the last descriptor of the frame. If the IC bit is set, Core10100 sets the transmit interrupt immediately after the
frame has been transmitted.
The int port remains LOW for a single clock cycle on every write to CSR5. This enables the use of both level- and edge-
triggered external interrupt controllers.
CSR11
Mitigation Control
TT = 0
NTP = 0
RT = 0
CSR5
Status
TI
RI
CSR7
Interrupt Enable
TIE
RIE
NRP = 0
TUE
TU
ERE
ERI
GTE
GTE
NIS
NIE
AIE
AIS
TSE
TPS
RSE
RPS
UNE
UNF
RUE
TU
ETE
ETI
Figure 4-9 · Interrupt Scheme
INT
56
v4.0
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