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| 型号： | CORE10/100-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 49/106页 |
| 文件大小： | 0K |
| 描述： | IP CORE10/100 ETHERNET MAC |
| 标准包装： | 1 |
| 系列： | * |
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Core10100 v4.0
Frame Data and Descriptors
Table 4-34 · CONTROL (TDES1) Bit Functions (continued)
Bit
TDES1.22
Symbol
FT0
Function
Filtering type
This bit, together with TDES0.28 (FT1), controls the current filtering mode.
This bit is valid only when the TDES1.27 (SET) bit is set.
Buffer 2 size
TDES1.(21..11) TBS2
Indicates the size, in bytes, of memory space used by the second data buffer. If it is zero,
Core10100 ignores the second data buffer and fetches the next data descriptor.
This bit is valid only when TDES1.24 (second address chained) is cleared.
Buffer 1 size
TDES1.(10..0)
Bit
TDES2.(31..0)
Bit
TDES3(31..0)
TBS1
Symbol
TBA1
Symbol
TBA2
Indicates the size, in bytes, of memory space used by the first data buffer. If it is 0,
Core10100 ignores the first data buffer and uses the second data buffer.
Table 4-35 · TBA1 (TDES2) Bit Functions
Function
Transmit buffer 1 address
Contains the address of the first data buffer. For the setup frame, this address must be
longword-aligned (TDES3.(1..0) = '00'). In all other cases, there are no restrictions on
buffer alignment.
Table 4-36 · TBA2 (TDES3) Bit Functions
Function
Transmit buffer 2 address
Contains the address of the second data buffer. There are no restrictions on buffer
alignment.
MAC Address and Setup Frames
The setup frames define addresses that are used for the receive address filtering process. These frames are never
transmitted on the Ethernet connection. They are used to fill the address filtering RAM. A valid setup frame must be
exactly 192 bytes long and must be allocated in a single buffer that is longword-aligned. TDESI.27 (setup frame
indicator) must be set. Both TDES1.29 (first descriptor) and TDES1.30 (last descriptor) must be cleared for the setup
frame. The FT1 and FT0 bits of the setup frame define the current filtering mode.
Table 4-37 on page 50 lists all possible combinations. Table 4-38 on page 50 shows the setup frame buffer format for
perfect filtering modes. Table 4-39 on page 51 shows the setup frame buffer for imperfect filtering modes. The setup
should be sent to Core10100 when Core10100 is in stop mode. When a RAM with more than 192 bytes is used for the
address filtering RAM, a setup frame with more than 192 bytes can be written into this memory to initialize its contents,
v4.0
49
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| CORE1553BBC-AR | 功能描述:IP MODULE CORE1553 BUS CTLR RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
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