参数资料
型号: CORE10/100-RM
厂商: Microsemi SoC
文件页数: 18/106页
文件大小: 0K
描述: IP CORE10/100 ETHERNET MAC
标准包装: 1
系列: *
Tool Flows
Core10100 v4.0
Simulation Flows
To run simulations, select the user testbench within the SmartDesign Core10100 configuration GUI, right-click, and
select Generate Design (see Figure 2-1 on page 16 ).
When SmartDesign generates the design files, it will install the appropriate testbench files. To run the simulation,
simply set the design root to the Core10100 instantiation in the Libero IDE design hierarchy pane and click the
Simulation icon in the Libero IDE Design Flow window. This will invoke Model Sim and automatically run the
simulation.
Synthesis in Libero IDE
Set the design root appropriately and click the Synthesis icon in the Libero IDE. The synthesis window appears,
displaying the Synplicity? project. Set Synplicity to use the Verilog 2001 standard if Verilog is being used. To perform
synthesis, click the Run icon.
“Timing Constraints” on page 70 details the recommended timing constraints that should be used during Synthesis.
Place-and-Route in Libero IDE
Having set the design route appropriately and run Synthesis, click the Layout icon in Libero IDE to invoke Designer.
Core10100 requires no special place-and-route settings.
“Timing Constraints” on page 70 details the recommended timing constraints that should be used during Layout.
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v4.0
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